Re: Put method in specific memory

From: Hans-Bernhard Broeker (broeker_at_physik.rwth-aachen.de)
Date: 06/08/04


Date: 8 Jun 2004 14:15:19 GMT

tom <xxx@xx.ve> wrote:

[...]

> Did I mention a loader ?

Well, you originally called it 'locator'...

> At the moment I am using a xilinx development board with a virtex II pro
> fpga with a powerpc405 on it. I am using the ise and the embedded
> development kit to configure the system. I am not using a OS, just
> developing a simple system with a powerpc, some memory and peripherals. More
> info needed ?

Probably not.

> > That said: if it can be done at all, then yes, a modification to the
> > linker script would have to be part of the trick. And some pretty
> > nasty pragmas or __attribute__(()) settings, too, to control it.

> Ok, that's what I want to know... can it be done ?

Quite probably. If you can control that locator, that is.

Others who know that particular platform will be able to help. As
might a look into the manual.

-- 
Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.


Relevant Pages

  • Re: FPGA area use by module?
    ... I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where ... the FPGA couldn't be routed anymore since it was too full. ... which ones use a lot of area so optimizing them would win me significant space. ... Is there a tool (or am I overlooking something in ISE) which tells me which ...
    (comp.arch.fpga)
  • Re: FPGA area use by module?
    ... Philip Herzog schrieb: ... I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where ... the FPGA couldn't be routed anymore since it was too full. ... Is there a tool (or am I overlooking something in ISE) which tells me which ...
    (comp.arch.fpga)
  • Re: clock problem
    ... I have a design which is supposed to run fine at 200mhz according to ... xilinx ise, but when i load the design to the fpga and try to run it ... use a slower clock, fpga gives the correct results,too. ...
    (comp.arch.fpga)
  • REPOST: Re: High Bandwidth Mixing Cipher Chips
    ... > Tom, you seem a bit rusty on FPGA size... ... One low cost development tactic is to bundle an FPGA with an embedded ... Newsgroups: sci.crypt ... NNTP-Posting-Host: 80.108.28.208 ...
    (sci.crypt)
  • Re: FPGA area use by module?
    ... I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where ... the FPGA couldn't be routed anymore since it was too full. ... Is there a tool (or am I overlooking something in ISE) which tells me which ... I have a small Perl script to do this at http://www.da.isy.liu.se/~ehliar/stuff/ ...
    (comp.arch.fpga)