H8/3867 Synchronous Uart False Clocks...

From: Paul Hackney (phackney_at_hanoverdisplays.com)
Date: 06/29/04

  • Next message: Dave Rooney: "Re: Mid '80s uP from Western Electric/AT&T -- WE212" 
    Date: Tue, 29 Jun 2004 12:34:57 +0100

    Does anybody know how to reset an H8 /3867 synchronous
    uart when it is part way through receiving a data byte?
    I have tried toggling the RE bit, apparently to no avail.

    I believe that noise may be causing a false clock so that
    the uart clocks in the first bit. Some period later, the
    real data is sent and the uart will raise RDRF after 7 bits
    have been received. One protection against this would be
    to reset the uart when expecting data. There is no obvious
    way that I can see to do this, except by toggling RE, but
    this appears not to work. Does anyone know if toggling
    RE does indeed reset the receiver? I guess there must be
    some kind of FSA which returns to its initial state after
    8 clocks. Is there any other way to persuade it to reset?

    Many thanks,

    Paul

  • Next message: Dave Rooney: "Re: Mid '80s uP from Western Electric/AT&T -- WE212"

    Relevant Pages

    • Re: H8/3867 Synchronous Uart False Clocks...
      ... An attempt to reset the uart, ... Why do I need to reset the receiver? ... >>I have tried toggling the RE bit, ...
      (comp.arch.embedded)
    • Re: H8/3867 Synchronous Uart False Clocks...
      ... How can you be sure that the time between toggling off and on again ... >the uart clocks in the first bit. ... Normally RE just enables/disables the receiver, it does NOT reset ...
      (comp.arch.embedded)
    • Re: 32 bit uart
      ... You can't use a standard rs232 type UART for this. ... The main problem would be in receiving: ... since you need to keep the receiver sampling point ... Of course, if the transmitting bit rate was fluctuating, then there is ...
      (comp.arch.embedded)
    • Re: shift reg 32bits
      ... always @ (posedge clk, posedge reset) ... Unless your UART has a FIFO, ... //reset all signals ...
      (comp.lang.verilog)
    • Re: [PATCH] sungem: Make PM of PHYs more reliable
      ... the PHY would be totally unresponsive even to toggling the hard ... > reset line until the machine is powered down... ... > -> msleep while I was at it to the pmac feature code that is called ...
      (Linux-Kernel)