Mixing address lines in SDRAM.

From: Wlad (whanski_at_wp.pl)
Date: 07/09/04 

Date: Fri, 09 Jul 2004 08:31:25 +0200

Dear all,

I have to boot-up a device based on Hitachi uP with external SDRAM
(2x256Mb). The device was designed by somebody else and I only have to
get it working. However there is something that bothers me very much.
Probably to easen PCB layout the designer has mixed data and address
lines for SDRAM: i.e. pin D0 of SDRAM is connected to pin D7 of uP. All
other interface signals (RAS#,CAS#,CLK,CKE,UDQM,LDQM,WE#,CE#) are
connected correctly. While mixing data lines seems ok to me (let me know
if I'm wrong) mixing address lines looks unacceptable.
Here are the connections:

SDRAM uP
------------------
A0 A5
A1 A4
A2 A3
A3 A2
A4 A14
A5 A13
A6 A12
A7 A11
A8 A10
A9 A9
A10 A6
A11 A8
A12 A7

BA0 A15 (bank select)
BA1 A16 (bank select)

Will this connection work? For the time being I know that I must forget
burst transfers. Are there any obstacles for SDRAM in this configuration
to work with 1-byte burst transfers?

Thanks
Wlad

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