Re: newbie: FIFOs and correlation algorithm in C for TI DSPs

From: sebastian (malaka_at_email.it)
Date: 08/21/04 

Date: 20 Aug 2004 15:23:26 -0700

"Brad Griffis" <bradgriffis@hotmail.com> wrote in message news:<rXIUc.3219$ZC7.1477@newssvr19.news.prodigy.com>...
>
> [BG] Not a chance! If you want to do processing at 100 MSPS you'll need a
> very powerful DSP. If you're doing communications you may want a digital
> down-converter chip between the ADC and the DSP. That chip will do a lot of
> the heavy duty filtering and demodulation to get you down to baseband. That
> will leave a more reasonable data rate for you to deal with in the DSP. You
> said you're an FPGA guy so why not put in a small relatively inexpensive
> FPGA to do the first part of the work and then do the rest on a DSP.

thanks for the suggestion, but what it made attractive the DSP was
it's FP capabilities, using the FPGA, i will implement my current
algorithms (not that there's anything wrong with that! :) ) but they
are "limited" in precision.
 
> I don't know if this will be of interest or not, but TI's 6416 DSP comes in
> speeds up to 1 GHz and has coprocessors for Turbo and Viterbi decoding. I
> think you can buy a 6416 DSP Starter Kit (DSK) from spectrum digital for
> $400 or so.
>

thanks! i saw it on TI's site too, it's very interesting for hobby,
too bad it has only audio codecs and not video.

>
> [BG] I think the compiler will often do this for you if you turn on
> optimization and set a inlining threshold. It's a tradeoff between code
> size and execution speed...

i need speed :)

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