XA-G49 (8051 extended architecture) I/O Port Bit-Addressing Question

From: Paul Marciano (pm940_at_yahoo.com)
Date: 11/30/04 

Date: 29 Nov 2004 17:08:14 -0800

Hi.

The P3 I/O port in my application has some bits used for output-only
and some for input-only. The output-only bits are configured in
push-pull mode and the input-only ones in quasi-bidirectional.

In quasi-bidirectional mode I have to write a '1' to the bit latch, so
as to not pull the line down myself.

My question: Can I use bit set/bit clear instructions (CLR, SETB) on
the output-only bits without clobbering the bit-latch for the input
bit?

If SETB/CLR are implemented as RMW, and the input value is zero, that
will clobber the latch, but if the SFR is truly bit-addressable at the
lowest level, then a bit operation won't clobber neighboring bits.

Here's an example to clarify my question:

  Suppose bit-7 is my input pin and bit 0 is my output pin.

  I want to set the output latch on bit 7 to '1' so as to allow the
  external device to drive it. I can do this with the instruction:

      setb P3.7

  If the device is currently driving the pin low, I'll get a zero
  in bit-7 if I read P3 back.

  Now say I want to drive out a '1' on my output bit, bit 0.
  I *could* do this with:

      setb P3.0

  But if this is implemented internally as a read-modify-write, it
  could do:

      P3 <- P3 OR 1

  As a read of P3 gives a zero in bit 7, this would clear bit 7,
  which is obviously undesired - my input bit is pulled low by the
  latch and that's the end of that.

  However, the chip implements:

      P3.0 <- 1

  Natively, then the P3.7 bit latch is untouched.

The XA User Manual does not specifically address this, although the
device is supposed to be operationally compatible with the 8051,
and I hope there are many 8051/XA-savvy people out there who could
help me out!

Thanks,
Paul.

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