Re: High speed USB 2.0 OTG component availability

From: Brad S (bjskill_at_rocketmail.com)
Date: 12/31/04 

Date: 30 Dec 2004 15:26:38 -0800

avrbasic wrote:
> "Brad S" <bjskill@rocketmail.com> wrote in message
> news:1104423466.699235.13340@c13g2000cwb.googlegroups.com...
> >
> [snip]
> > Antti -
> >
> > Approximately how many FPGA gates would the USB 3300 IP core
solution
> > consume? Also, when this IP core is inserted and compiled for the
FPGA
> > what clock speeds will be required in order to reduce the
possibility
> > of internal timing problems?
> >
> > We have an FPGA available that will be used for several other
functions
> > but it's currently unclear how many gates will be available for
this IP
> > core or any other additional functions.
> >
> > Brad S.
>
> usb3300 is an ULPI PHY (similar to ISP1504) not ip-core.
> I have not seen any real small USB OTG IP Core solutions, and I also
have
> never synthesised usb ip-cores as standalone only as part of FPGA
softcore
> SoC system.
>
> my thumb guess would be that if your FPGA is S3-1500 or anything
similar
> then you might have enough resources overleft. A 32 bit softcore RISC
> (microblaze) + some bus peripherals + hs usb ip core takes more than
60% of
> V2-1000. Thats my best estimates if those would help you. I dont
think there
> is any usbhs otg ipcore really optimized for FPGA so its not yet cost
> effective option. For ASICs the gate-cost is smaller so its not such
an
> issue.
>
> Antti
> news:openchip.org

Antti -

Thanks for the estimates. I didn't realize that the usb3300 was the
ULPI PHY and had nothing to do with the ip-core. Thanks for the
clarification.

It sounds like an FPGA-based solution isn't a cost-effective solution
at this time. Developing an ASIC is not an option for us, so we will
have to stay with any commercial USB hosting devices that become
available in the near term.

Brad.

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