Re: AVR interrupt response time

From: CBFalconer (cbfalconer_at_yahoo.com)
Date: 01/13/05 

Date: Wed, 12 Jan 2005 23:04:26 GMT

Jeroen wrote:
> "Pygmi" <bronco_castor@hotmail.com> wrote in message
>
>> I just started my first time critical project with AVR's.
>> And time critical meaning interrupt response times.
>> So far I have been using avr-gcc (3.3.x) and I have been
>> pretty happy with it. And I have written ALL code in C.
>>
>> I'm hoping to get some code executed within 2 us or so
>> after external interrupt (INT0/INT1 with ATMega32).
>> I wrote the code to be executed today and ended up to
>> appr. 20 instructions/cycles. With 16 MHz clock that
>> means something like 1.25 us. Nothing much to optimize
>> there.
>>
>> From datasheets I have found out that it takes 4 cycles
>> minimum (?) to jump to interrupt handler. By adding some
>> register saving and stuff, I was expecting less than 0.5 us
>> to start executing my own code => resulting in <2 us.
>>
>> Ok, that was what I was hoping...
>>
>> When I compiled the code and ran it, I noticed that it
>> took about 2.5 us to start executing my code?!?!
>> (I used ATMega8 as I don't have any M32 at the
>> moment, but I guess it isn't relevant??)
>> I checked the list file and one reason is the
>> LENGHTY prologue added by gcc into interrupt
>> handler (17 instructions!!!), saving LOT of registers...
>>
>> Two questions:
>> 1. Even with 4 cycles + 17 instructions there is 1 us
>> missing?? What else happens before my own handler
>> code starts executing?
>> 2. Is there any way to tell gcc NOT to 'push' all those
>> registers in to the prologue??
>>
> > And finally:
>> If I expect to have my own code to execute
>> within 0.5 us, is the assembler the only way to go??
>
> The processor first synchronizes the external input to it's own
> clock, that's takes at 2 clocks. The processor also has to finish
> the currently executing instruction. It takes 3 cyles to go the
> interrupt vector, from where it executes a jump to your ISR,
> another 3 cycles. This is 8 cycles to 11 cycles total time,
> depending on the executing instruction; or 0.6875 us. Then it has
> entered your ISR; you at least need to save the statusregister
> and a few registers before useful work can be done.
>
> How did you check the response time? With a scope?
>
> Assembly will be neccesary if you want to sqeeze out every last
> bit of performance. What's the application that this is so
> critical?

And all that assumes that the executing code has no critical
sections implemented by disabling interrupts. Does no ARM
instruction take over 3 cycles? What about a return? What about
other interrupts and returns from them, if any. Hairy. 

-- 
Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
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