Re: Cell Architecture Explained (MASSIVE AMOUNT OF INFO)
From: Robert Myers (rmyers1400_at_comcast.net)
Date: Sat, 22 Jan 2005 09:53:57 -0500
On Sat, 22 Jan 2005 01:53:48 GMT, Maynard Handley <firstname.lastname@example.org>
>In article <QvadnatFwfzw6W3cRVnemail@example.com>,
> "Xenon" <firstname.lastname@example.org> wrote:
>> The lack of cache and virtual memory systems means the APUs operate in a
>> different way from conventional CPUs. This will likely make them harder to
>> program but they have been designed this way to reduce complexity and
>> increase performance.
>You don't say.
>Programming Itanic was a picnic compared to programming this thing; at
>least Itanic used a traditional computer architecture.
>And yet Intel/HP, with all the money in the world, couldn't make it fly.
>Please tell us why IBM/Sony/Toshiba can do what Intel/HP could not.
Itanium and Cell both offer advantages for problems that can be
formulated to exploit the architecture. In the case of Itanium, the
advantages have turned out not to be overwhelming. In the case of
stream processors, there are already off-the-shelf GPU's that can
significantly outperform any conventional microprocessor for some
kinds of problems, and the advantage of stream processors will only
grow as feature sizes decrease.
>(Note, I am not denying that Cell may make a fine Playstation chip.
>I AM denying that it will make a fine workstation chip, will take over
>the computing world, make all other CPUs obsolete, blah blah blah.)
Predicting the future is really hard. Genuine paradigm shifts are
rare, but I think this one is on its way. The future of computing is
more like what happens on network processors and GPU's than what
happens on x86, PowerPC, or Itanium. The change is being driven by
physics, not marketing.
>> This may sound like an inflexible system which will be complex to program
>> and it most likely is but this system will deliver data to the APU registers
>So in return for giving up cache, your code has to manually move data
>to/from memory. That'll be easy for the compiler to figure out.
Of course it won't. But the same problem exists--how do I figure out
how to get the data to where I need it when I need it?--in any
architecture. Cache and registers add a set of tools for dealing with
that problem; they don't make it go away. In the case of at least
some stream processors, there is a _register_ hierarchy: a
low-bandwidth stream register file that faces memory and local
register files that act much like a conventional vector register.
>There's (much much, so much) more blather and ranting about how how
>fantastic Cell is and how it will solve any problem you can possibly
>imagine, but for those of us in the reality-based community, I think the
>points I have extracted above are the highlights.
>Bottom line is that this thing doesn't resemble any traditional CPU and
>is therefore a godawful match to existing languages, compilers and
>algorithms. Unless IBM/Sony/Toshiba have, in some other pocket, and kept
>an extremely good secret that solves problems many people have been
>working on for more than twenty years, you'll be programming this thing
>with an assembly language mindset, even if you are nominally using a
>high-level language --- like you program AltiVec today. Only it'll be so
>much more fun because not only will you be worrying about alignment and
>algorithm issues, you'll be trying to juggle fitting your instructions
>and data into local memory (we weren't given a size for this but if it
>is to run at L1 cache speeds, it can't be wildly far off from say 64K to
>512K bytes); none of that getting the cache to just hide the problem for
>you if you might want to load from an infrequent used table, handle a
>rare exception condition or whatever; it'll be manual segment swapping
>all over again. Not to mention the other glorious aspects. You'll be
>using some bizarro method to handle coherency. You'll have the engine
>that drives your code and handles exceptions and such running on a
>different processor from where the compute intensive code lives.
Maybe. Somebody likes programming these things because people are
already doing it--just for fun, apparently.
The problems are formidable, but it is early days yet when it comes to
inventing programming models and algorithms for stream processors.
One future I can see is that data (and instructions) will no longer be
associated with memory locations but with labelled packets.
There will always be something that looks like a conventional
microprocessor? Let's wait and see what the promised workstations
look like. Weren't we supposed to have seen them last fall?
The one thing in all this that _really_ gives me pause is that making
it work in the general case seems like getting a dataflow machine to
work in the general case.
There's a really nice summary of GPU programming entering the
>And all this from IBM/Sony/Toshiba, three companies traditionally known
>for their openness and willingness to share with the public. I imagine
>Intel, AMD and Microsoft are quaking in their boots.
They couldn't possibly be less open than the graphics card
manufacturers have been.