Proper way to set up boot.s and gnu linker script for ARM / AT91R4008 / EB40A?

From: James Johnson (jj_at_yaaho.com)
Date: 02/01/05


Date: Tue, 01 Feb 2005 12:00:50 -0500


I'm using the Atmel AT91R4008 on the eb40a evaluation board. I have a
lot of things working on this system, but need to understand the best
way to set up the linker script and boot.s. Here's what I have so far.

BOOT.S:
============

.section .text
.code 32
.global vectors
.global und_stack
.global abort_stack
.global fiq_stack
.global irq_stack
.global svc_stack
.global sys_stack

.set MODE_FIQ, 0x11 @ FIQ Mode
.set MODE_IRQ, 0x12 @ IRQ Mode
.set MODE_SVC, 0x13 @ Supervisor Mode
.set MODE_ABT, 0x17 @ Abort Mode
.set MODE_UND, 0x1B @ Undefined Mode
.set MODE_SYS, 0x1F @ System Mode
.set MODE_USER, 0x10 @ User Mode

.equ F_BIT, 0x40
.equ I_BIT, 0x80

.equ UND_STACK_SIZE, 256
.equ ABT_STACK_SIZE, 256
.equ FIQ_STACK_SIZE, 256
.equ IRQ_STACK_SIZE, 2048
.equ SVC_STACK_SIZE, 2048
.equ SYS_STACK_SIZE, 8192

vectors:
        b reset @ 0x00 Reset
        b exception @ 0x04 Undefined instruction
        b exception @ 0x08 SWI
        b exception @ 0xc0 Prefetch abort
        b exception @ 0x10 Data abort
        b exception @ 0x14 reserved vector
        ldr pc, [pc, # -0xF20] @ 0x18 irqs fffff100 (AIC_IVR)
        b exception @ 0x1c fast irqs

exception: @ 0x20
        b exception

reset:
        msr CPSR_c, #MODE_UND|I_BIT|F_BIT
        adrl sp, und_stack+UND_STACK_SIZE

        msr CPSR_c, #MODE_ABT|I_BIT|F_BIT
        adrl sp, abort_stack+ABT_STACK_SIZE

        msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT
        adrl sp, fiq_stack+FIQ_STACK_SIZE

        msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT
        adrl sp, irq_stack+IRQ_STACK_SIZE

        msr CPSR_c, #MODE_SVC|I_BIT|F_BIT
        adrl sp, svc_stack+SVC_STACK_SIZE

        msr CPSR_c, #MODE_SYS|I_BIT|F_BIT
        adrl sp, sys_stack+SYS_STACK_SIZE

        bl main

        b vectors

und_stack: .space UND_STACK_SIZE, 0
abort_stack: .space ABT_STACK_SIZE, 0
fiq_stack: .space FIQ_STACK_SIZE, 0
irq_stack: .space IRQ_STACK_SIZE, 0
svc_stack: .space SVC_STACK_SIZE, 0
sys_stack: .space SYS_STACK_SIZE, 0

        .end

RAM.LD:
==============

ENTRY(vectors)

SEARCH_DIR(.)

MEMORY {
   sram : org = 0x00000000, len = 256K
}

SECTIONS {
   .text : {
           *(.text);
           . = ALIGN(4);
   } > sram

   .data ADDR(.text) + SIZEOF(.text) : {
      datastart = .;
      __data_start__ = . ;
      *(.data)
      . = ALIGN(4);
      __data_end__ = . ;
      edata = .;
      _edata = .;
   } > sram

   .bss ADDR(.data) + SIZEOF(.data) : {
      . = ALIGN(4);
      __bss_start__ = . ;
      *(.bss);
      *(COMMON)
      __bss_end__ = . ;
      . = ALIGN(4);
   } > sram

   .rodata ADDR(.bss) + SIZEOF(.bss) : {
      *(.rodata*)
      . = ALIGN(16);
   } > sram

   .heap ADDR(.rodata) + SIZEOF(.rodata) : {
      _heap_start = .;
      . += 0x800;
      _heap_end = . ;
   } > sram

   .stack ADDR(.heap) + SIZEOF(.heap) : {
      . = ALIGN(16);
      _stack_bottom = . ;
      *(.stack);
      _stack_top = . ;
   } > sram

   end = .;
   _end = .;
   __end__ = .;

   .stab 0 (NOLOAD) : {
      [ .stab ]
   }

   .stabstr 0 (NOLOAD) : {
      [ .stabstr ]
   }
}