Re: PPC405 sleep?
From: newman5382 (newman5382_at_yahoo.com)
Date: 02/21/05
- Next message: RichH: "Univeral Programmers"
- Previous message: Bo: "Re: PPC405 sleep?"
- In reply to: Bo: "Re: PPC405 sleep?"
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
Date: Mon, 21 Feb 2005 15:44:30 GMT
"Bo" <bo@cephus.com> wrote in message
news:Y9nSd.1103$i32.86@fe40.usenetserver.com...
> We discovered the source of our 'cant wake up' problems late Friday....
> unfortunately, I have not determined how, or even if, the problem can be
> or should be circumvented....
>
> Here's the story of what was/is:
>
>
> 1)We put uP to sleep
>
>
> 2)An ext int happens.
>
>
> 3)The uP wakes up:
>
> 3a)Stores the context, all regs, etc on his ISR context stack--
> including MSR register.
>
> 3b)We mod the TCR to re-enable timer interrupts
>
> 3c)The ISR is serviced
>
> 3d)The original context is restored.
>
> 4)Now, we're back asleep since orig context is restored.
>
>
> So we're continuously being put back to sleep and our mods to the TCR/MSR
> are promptly overwritten by the ISR context restore at the interrupt exit.
> We tried modifying SRR1 in the ISR to clear the WE bit--but that doesn't
> work. It apparently uses the ISR stack context copy and then restores SRR1
> from the stack, then SRR1 to MSR upon rfi.
>
> I'm looking at how to circumvent it in asm. Your thoughts?
>
> I understand some VHDL needs to be written for a full implementation of
> power management--but I'm not at all sure how it is all supposed to play
> together. I read about the sleep req and other signals--but I don't follow
> how this comes into play with the level of management I am currently
> trying to get working. The VHDL does make sense to me when you start
> actually physically changing clk freq or disabling clk into the 405 core.
> An example from Xilinx is apparently too much to hope for... to my and my
> FAE's knowledge there are no CPM examples or std. CPM core--not even for
> their ML310 development boards, but I digress.
>
> As an aside, I cannot seem to find an asm instruction that allows you to
> store the contents of a given register at a desired location (ie offset
> from stack context register R31). In other words, what instruction would I
> use to store contents of R20 at address specified by (R31 + offset)? And
> the doc from Xilinx does not have all instructions that the compiler is
> generating (like "lis").
>
> Paul
I don't pretend to completely comprehend what you found, but I think a "Nice
Catch" is in order.
I saw in the ppc_ref_guide.pdf that
lis has an equivalent mnemonic addlis page 534. The user is required to
skip around this document to look up a simple thing, and it is quite
annoying.
-Newman
- Next message: RichH: "Univeral Programmers"
- Previous message: Bo: "Re: PPC405 sleep?"
- In reply to: Bo: "Re: PPC405 sleep?"
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
Relevant Pages
|
