Re: Interrupt Question
From: James Beck (jim_at_reallykillersystems.com)
Date: Fri, 25 Feb 2005 15:13:21 GMT
In article <email@example.com>,
> Mike Harding <firstname.lastname@example.org> wrote:
> >>Many methods have been described in this thread that can
> >>minimize this ambiguity. Most of them have been used to solve
> >>this problem in the real world but the only deterministic
> >>solution is to change the problem.
> >Like... stop interrupts for a bit?
> Disabling interrupts can not fix the problem only reduce the occurrence
> rate. If it was homework you would be getting a D.
> A high priority interrupt which depends on data generated in a low priority
> interrupt is a contradiction. Probably the result of fuzzy thinking in the
> system design or hardware restrictions.
> If the interrupt priorities can be exchanged the solution is simple,
> otherwise some other agent is needed to help the high priority interrupt
> know the validity of data from the other or to do the work of the other in
> a different way.
I would think that the solution is very hardware dependent.
If the processor in question requires that an ISR re-enable ints if
there is to be pre-emption by higher priority interrupts then there is
no problem. Even thought ISR2 is a higher priority it can be blocked by
ISR1 just by not enabling INTs in the routine. If the processor in
question guarantees that the at least one instruction is executed in an
ISR when it has occurred then make the first instruction a disable
interrupts. Basically you need to use some way to temporarily raise the
priority of ISR1 or consider it a critical section and block other INTs.
You gotta' do a Kirk and change the parameters of the test ;).