Re: Understanding DMA

From: Rufus V. Smith (nospam_at_nospam.com)
Date: 03/24/05 

Date: Thu, 24 Mar 2005 15:41:12 -0500

"steve" <mister.steve.smith@gmail.com> wrote in message
news:1111694057.215005.29810@f14g2000cwb.googlegroups.com...
> What I understand about DMA is that the CPU is idle during DMA cycles.
> If this is true whats the use of DMA. I cant find the advantage of
> 'offloading' the data transfer to the DMA controller if the CPU cant
> use that time to do something else . My 2nd question is : Lets assume
> that the CPU is not idle during DMA cycles. In that case, the cpu cant
> access memory so it cant fetch instructions/data so how does it do
> useful work?
> thanks

Your understanding is only partly true. The CPU doesn't necessarily have
to be idle during DMA cycles, just not contending for the bus. And this
doesn't happen for the entire data block, just byte by byte (or word by
word, or whatever burst your system uses).

Typically DMA cycles fit "in between" CPU memory access cycles. CPUs do
other things besides reading and writing to memory, particularly ones
with onboard cache (although this raises other issues about mem. access).

Of course, if you are the system designer, you design memory access in
pages,
such that you are DMA-ing into one page while the processor code runs in
another, and avoid conflicts completely.

DMA does also not necessarily run at processor speed. You could have a
device that is delivering, say, 1 byte per microsecond, while your cpu
is on a 100ns clock. You may get several instructions between DMA
accesses. Use this time for "useful" work.

You can google for more info.

Rufus

Relevant Pages

  • Understanding DMA
    ... What I understand about DMA is that the CPU is idle during DMA cycles. ... 'offloading' the data transfer to the DMA controller if the CPU cant ...
    (comp.arch.embedded)
  • Re: A simple question about DMA, please help me.
    ... held by the DMA controller and the CPU is set idle until this transfer ... memory to fetch instructions while the DMA transfer is continuing. ... The PCI bus changed that -- it eliminated the separate lines for each ...
    (comp.lang.asm.x86)
  • Re: Volatile variables
    ... I/O methods ("DMA" and the like) that completely bypass the CPU. ... then DMA bypasses the on-chip cache. ... memory. ...
    (comp.lang.c)
  • Re: performance problem
    ... DMA is enabled on all drives. ... USER PID %CPU %MEM VSZ RSS TTY STAT START TIME COMMAND ... > problematic daemon running. ...
    (Debian-User)
  • PROBLEM: DMA over CPU" memory leak in Kernel 2.6.8.1
    ... "DMA over CPU" memory leak if I burn Audio-CDs ... d0000000-dfffffff: PCI Bus #01 ...
    (Linux-Kernel)