Re: 24-bit SPI?
- From: David <david.nospam@xxxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Thu, 28 Apr 2005 15:23:04 +0200
On Thu, 28 Apr 2005 08:48:21 -0400, Ryan wrote:
>
> "David" <david.nospam@xxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
> news:pan.2005.04.28.07.23.11.218000@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx
>> On Thu, 28 Apr 2005 08:16:15 +0200, orc wrote:
>>
>> > "David" <david.nospam@xxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message:
>> >> The usual method is to send three 8-bit transfers after each other,
>> >> holding the chip select low during the transfer. Some SPI controllers
>> >> (don't know about ARM chips) can do this automatically, but it's still
>> >> just a series of standard 8-bit transfers.
>> >
>> > Thanks. Most ARM controllers has both 8 and 16 bit SPI lenght because of
>> > efficiency (16 bit) (which is needed in my application) so that the
>> > controllers hasn't to put the three 8 bits together in a long var.
> manually
>> > (rotating and OR-ring). An alternativ question: is there somehow a
> better
>> > way to join the fractions into a 32 bit long (e.g. is the DMA controller
>> > able to transfer the data from the SPI and access the memory in 8 bit
>> > portions)?
>> >
>> > Any help is highly appreciated.
>>
>> I don't remember whether the ARM is big-endian or little-endian, but a
>> common way to merge bytes into a long is to use a union :
>> typedef union {
>> struct { unsigned char lolo, lohi, hilo, hihi; } bytes;
>> unsigned long longword;
>> } merger;
>>
>> Anyway, if your application can't afford the time taken to calculate
>> "(hilo << 16) | (lohi << 8) | lolo" after reading the data, then you
>> really need to think about what you are trying to do here, and whether you
>> are going about it the right way.
>>
>>
>>
>
> If you have an exceptionally large number of components communicating via
> SPI with abnormally high data rates, I could see where <<16 and <<8 could be
> a performance penalty. This is an embedded newsgroup; I would bet a good
> number of people here are examining their resulting assembly code and
> getting the most out of every cycle.
>
> -R
I know this is an embedded newsgroup, and I know all about examining
assembly code and counting cycles, and when it is a useful tool and when
it is not. If it becomes essential to count the cpu cycles when
transferring SPI bytes, even at the highest SPI rates (20 MHz?), at this
stage of the design (i.e., trying to guess which chip to use), then it is
time to look closely at the design and the requirements, because you are
doing something badly wrong.
.
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