Re: 8051 architecture question

"JBrewster" <john@xxxxxxxxxxxxx> wrote in message

> I've been through a couple of 8051 tutorials but still have a very
> fuzzy view of its architecture.
>
> Could someone draw me a simple view of it.

Assuming a basic 8051 (not a '52, no internal flash or whatever):

--
There is 64Kbyte of program space, and 64Kbyte of data space.
The program space is read-only and enabled by the CPU's #PSEN
line; the data space is read-write and enabled by the CPU's
#RD and #WR lines.

You can hold read-only constant data in program space, but you are limited
as to the instructions and/or addressing modes by which that
can be accessed. The assembler instructions used determine which
space to deal with: MOVX refers to data space, and MOVC refers
to program space.

There is, of course, nothing to stop you hardware mapping
the same physical memory (or a subset of it) so that it appears
in both data (MOVX) and code (MOVC) space.

--

The 8051 has 256 bytes of internal on-chip "memory", independent
from the 2*64K*8 mentioned above. However, only the bottom 128
bytes is actual memory (holding register banks, bit-addressable
memory, the stack, and everything else). The upper 128 bytes
is actual special function registers.

You gain access to this 256 bytes using yet more (different)
instructions. The upper 128 (the SFRs) can only be accessed
using direct addressing (no indirection)

--

The '52 variants (usually) have a real 256 bytes of internal
memory, in addition to the 128 bytes of SFRs, whose space they
overlap: when dealing with this upper 128 bytes, you use direct
addressing to get the SFRs and indirect addressing to get the
upper 128 bytes of real memory.

--

Then, there are processors which have onboard RAM which appears
as external RAM (in MOVX space). You use MOVX instructions
even though the RAM is physically on-chip: you have to set
config registers and/or hardware pins to select whether you
want addresses in the appropriate MOVX region to map to "real MOVX
RAM" or "internal MOVX RAM". Some processors will still generate
an external bus cycle even when dealing with onchip RAM in this
manner.

--

Most 8051 variants these days have onboard flash/otp/rom: this
internal ROM (in preference to accessing external MOVC space)
is selected using the #EA pin.

Richard [in PE12]


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