Re: how to generate time delay

Thanks all for your input. My intention is to generate a digital
pulse train using hardware logic chips. (I am trying to create
hardware to read a ROM and load into RAM. I am using the datasheet
from a 93C46 eeprom, as that is cheap and small and is all I will
need.)

I now understand there must be a better way than using one-shots to
generate a delay.
By further quantizing the signals by using various dividers off of a
single clock I have reduced my problem to one: I still need a delay,
but now it can be treated as a phase offset. So, if I have signal A
and signal B of the same frequency, how can I make signal B be out of
phase by 180 degrees.

(The differentation using the inverter shows two inputs to the
inverter. I don't understand that? And where is the clock into the
flip-flop?)

Thanks again,
JD

.

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