Re: how to generate time delay




Jim Granville wrote:
> Why not use a small CPLD, for this task ? - there are examples of
> CPLDs for loading the RAM in FPGAs, from SPI memory.
>
> How are you building the psuedo-CPU ?


I'm doing the control unit first, most of which will be as a state
machine stored in an eeprom (which will first be loaded into ram). But
I don't want to use a microcontroller. I want the hardware circuitry
to load the serial eeprom to ram. If I can accomplish that much, then
I'm sure I can design and build circuitry to step through the ram
addresses that will contain the state machine that acts as the control
unit.

I say "pseudo-CPU" because at this point I want to build merely the
control unit that will generate a set of desired waveforms. Those
waveforms are fairly complex and I would not dream of doing them
without a micro-coded/micro-sequenced process using eprom. However,
the waveforms to generate signals to read a serial eeprom into RAM are
much simpler and I am very close to a hardware design that I *think*
will work. (I'm using very slow clock frequencies and making all my
divisions multiples of that freq. Someone mentioned quantizing the
signal, I think thats what I am doing.)

IF examples existed for loading eprom into RAM and IF PLDs can be
programmed as easily as eproms apparently are (i.e. by hand or by PC
parallel port; a dedicated programmer is out of my budget range), then
maybe a PLD would be a possibility. I'll look into that.

Thanks,
JD

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