Re: Confused with "task" keyword.

On Tue, 26 Jul 2005 21:37:57 +0800, Confused Frank wrote:

> I wrote a task to feed test vectors to my design, however, I realized some
> differences between
> "task" and the normal state machines I used to do. One sample code below, I
> am expecting the
> the signal "trd_sample" to be delayed by one cycle of "trc", i.e. 2nd
> posedge of trc. However,
> why does the simulation shows on the first posedge of trc?
>

Frank,
I am confused as to what behavior you are expecting. Your always@ block
at the end will make trd_sample equal to trd every time that there is a
posedge of trc. Since you are using non-blocking assigments, the signals
are assigned immediately, with no regards to clocks. That also means
that there is also no 'guarantee' of the order of assignment either. When
you have three non-blocking assignments in sequence, the simulator might
not execute them in the same order as written, generating some
interesting race conditions.

Chuck
.

Relevant Pages

  • Re: Confused with "task" keyword.
    ... >> posedge of trc. ... >> why does the simulation shows on the first posedge of trc? ... > I am confused as to what behavior you are expecting. ... > that there is also no 'guarantee' of the order of assignment either. ...
    (comp.arch.embedded)
  • Re: ordering in Verilog
    ... I thought this would cause a glitch if the next ... if there is no other assignment below. ... always @ (posedge clk) style blocks for synthesis. ... always @(posedge clock or posedge reset) ...
    (comp.lang.verilog)