Enable/Disable cache on MIPS
Hi,
I am working on a MIPS 4KSd core, and I'm having trouble understanding
what operation code to use for the cache instruction. I read somewhere
that 'Hit type' is generally used for running cache maintainence, and
'Index Type' is used for initialization. Does invalidate, flush,
enable/disable and lock come under maintainence?
I am trying to enable/disable instruction and data cache, and I don't
see what op code I need to use.
For example in ARM, we can just do it in a read-modify-write sequence.
Eg. To disable I cache
MRC p15,0,r0,c1,c0,0 ; read CP15 register 1 into
r0
BIC r0,r0,#(0x1 <<12) ; Disable I Cache
MCR p15,0,r0,c1,c0,0 ; write value back
How do I go about doing this on a MIPS processor?
Any help would be appreciated.
Thanks,
Larina
.
Relevant Pages
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... what operation code to use for the cache instruction. ... How do I go about doing this on a MIPS processor? ...
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(comp.sys.arm) |
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