Re: Octal switches: Maximising MCU pin usage with data busses
- From: "techie_alison" <techie_alison@xxxxxxxxx>
- Date: Tue, 25 Oct 2005 16:25:58 +0000 (UTC)
"James Beck" <jim@xxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:MPG.1dc81cbec4ab0760989baa@xxxxxxxxxxxxxxxxxxxxxxxxxx
> In article <djj13r$4uu$1@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>,
> techie_alison@xxxxxxxxx says...
> > Hello,
> >
> > I hope you can help, I'll try to explain what I'm trying to do rather
than
> > what I want..
> >
> > I'm working with the 16F877A and need to interface to several data
busses
> > and minimise on single pin usage, each width being 8 bits, well one is
16
> > bits wide but I can treat that as two 8 bit interfaces and load one and
then
> > the other (I hope). It would be useful if the outer latches maintained
> > their values when switching to the next switch 'chip'. CS
> >
> > The ideal scenario would be to have a single port (PORTA?) interfaced to
all
> > of the chips, and say PORTB selecting the individual chips.
> >
> > I've seen in the older reference manuals (early 1990's) mentions of
chips
> > that could possibly do this, described as 8-pole / octal 'digital'
switches
> > and with 40P/DIP profile. Response time being at about 7nS or so. 10nS
to
> > 50nS response time would be fine.
> >
> > Before I go, I have to use the 16F877 as we have a bit of stock of these
and
> > this is a prototype project, also I'm running at 20Mhz / 200nS
instruction
> > speed.
> >
> > Thanks in anticipation of any help you can provide,
> >
> > techie_a
> >
> >
> >
> Many I/O bound designs have used the concept of a pseudo address and
> pseudo data busses. Use one port as a bidirectional data buss, do NOT
> use the PORTA on a PIC unless you confirm that bit 4 is not an open
> collector style output (it is on the 877), and another port as a
> control/address buss. The trick is to come up with some routines to
> keep the signal timings sane as to not have a buss contention when
> switching from read to write and so on.
>
> Jim
Hi James,
Thanks for replying, yep will go with things as they come.
I'm presently looking at a central bus to run right through the project,
something like this;
http://server.barrymichels.com/ide/
The 373 latches I think are there to hold the memory address in place while
the RAM is written. So the operation would be to set the RAM address, lock
the latches, fetch the byte, dump it in ram, and then move onto the next
byte / word.
In some ways I'm tempted to do away with the RAM and latches, as I don't
really need to process the information or have it in the PIC, just to pass
it back n forth. Say pull a word from the IDE port, and dump it out as 2
bytes to the SCSI-1 non-parity variant. All in real time.
This is very much an information gathering excercise.
Aly :-)
.
- References:
- Octal switches: Maximising MCU pin usage with data busses
- From: techie_alison
- Re: Octal switches: Maximising MCU pin usage with data busses
- From: James Beck
- Octal switches: Maximising MCU pin usage with data busses
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