Persistent stall in the Cypress FX2 FIFO

Hi all,
I am using the Cypress FX2 to interface an FPGA to a PC via an
USB2.0 link. The FX2 was configured to provide 4 bulk endpoints
(+ synchronous FIFOs). Each bulk EP (2,4,6,8) is 512 byte long
and is double buffered.
All seems to work quite fine, but when a FIFO get full (i.e. the PC
send more than 512 bytes) the EP does not take data any more,
even if the FPGA empty the FIFO!
The endpoint seems to be stalled, but the stall flag in the EPxCS
register is cleared. I tryed also to reset the pipe or to send a Clear
Feature message, but nothing succeed in unlocking this "stall"
condition. What else should i try?!?
Any help is highly appreciated!
TIA

A.D.






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