Re: Persistent stall in the Cypress FX2 FIFO
- From: "Antti Keskinen" <antti.keskinen@xxxxxxxxx>
- Date: Mon, 21 Nov 2005 11:18:27 +0200
Hello !
Are you absolutely certain that the endpoint is STALLed ? STALL condition
usually means that the endpoint has received an invalid USB request. In this
case, and looking at the FX2 TRM, it might mean you're not serving the IBN
and PING requests sent by the host.
For example, the host sends you a BULK OUT packet with more data than you
can handle in one transfer. First, the DATA IN interrupt of the appropriate
endpoint is set, and you service it properly to receive the data and clear
the master interrupt (INT2IRQ) and the individual interrupt register. This
is all well and good, and is done precisely the same way for transfers which
are below the limit.
However, when more data is sent in while the buffer is still full (sending
more than 512 bytes), the firmware responds with a NAK signal to the host to
any further sends. This indicates that the endpoint cannot receive any more
data, and in USB 2.0 environment, it instructs the host to start sending
PING requests instead. A PING request is much like asking "are you ready yet
?", and is used instead of multiple NAK returns to conserve bandwidth.
In your scenario, it might be possible that after the NAK signal is sent
back to the host, you're not serving the PING/IBN interrupts generated by
the firmware. If you do not serve these interrupts (clear them), the
firmware most likely STALLs the endpoint to indicate that it has received a
request that was not served (i.e. an unsupported USB request). Since the
host is constantly sending the PING packet to you, and you're not serving
it, the endpoint stays STALLed for ever more, regardless of you clearing or
resetting the endpoint.
See the FX2 TRM for instructions on how to serve the PING interrupt (Chapter
8.6.3.1.). If this helps you solve the issue, post back to these boards to
indicate that it was the culprit. This indication helps others who're
wrestling with the same problem
Greetings,
Antti Keskinen
----- Original Message -----
From: "A.D." <stevenson@xxxxxxxxxxx>
Newsgroups: comp.arch.embedded
Sent: Sunday, November 20, 2005 6:28 PM
Subject: Persistent stall in the Cypress FX2 FIFO
> Hi all,
> I am using the Cypress FX2 to interface an FPGA to a PC via an
> USB2.0 link. The FX2 was configured to provide 4 bulk endpoints
> (+ synchronous FIFOs). Each bulk EP (2,4,6,8) is 512 byte long
> and is double buffered.
> All seems to work quite fine, but when a FIFO get full (i.e. the PC
> send more than 512 bytes) the EP does not take data any more,
> even if the FPGA empty the FIFO!
> The endpoint seems to be stalled, but the stall flag in the EPxCS
> register is cleared. I tryed also to reset the pipe or to send a Clear
> Feature message, but nothing succeed in unlocking this "stall"
> condition. What else should i try?!?
> Any help is highly appreciated!
> TIA
>
> A.D.
.
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