AT91RM9200/Davicom and Altima phy compability
- From: "devlin" <e4borgen@xxxxxxxxx>
- Date: 30 Nov 2005 15:28:21 -0800
Hello,
We're having two ethernet problems with an Atmel AT91RM9200 CPU
based construction. I'm interested if we are the only one
having these problems...
Our first attempt were to use a 16MHz crystal and the AT91 built-in
PLL and programable clocks to generate the required
50Mhz and 25Mhz needed for a Davicom DM9161 PHY and a Davicom
DM9000 10/100 ethernet controller (thus giving us two ethernet).
Somehow this were not very successful - TFTP and ping worked decent at
100mbit when running u-boot (bootloader with interrupts/mmu etc.
disabled)
But somewhere during the linux boot the network activity led
started to flash rapidly - using an oscilloscope it seemed to
jump to 10mbit every second and then back to 100mbit mode
(but with very random and few packets getting through).
Forcing it to 10mbit half duplex made it work better but not
reliably.
What went wrong here ? Are the PLLs just not good enogh to use
as a reference for a 50Mhz ethernet PHY / 25MHz eth. controller ?
Using cross-over cable and different ethernet boards in the other
end gave somewhere between 20-100% packetloss on ping packets.
Well...
Skipping the PLL and using a 50Mhz oscillator instead gave us
a better reliability on both of the ethernet circuits.
We have reliable 100mbit half/full communication on both
davicom circuits - but we are not able to talk to devices with an
Altima AC101 PHY circuit unless we use 10mbit half duplex.
The same problem has been observed on the Atmel AT91RM9200-EK board
which also uses the Davicom DM9161 PHY.
Has anyone else noticed that the Davicom and Altima circuits are
incompatible ?
Is there a 'compability' matrix of different PHY manufacturers ?
Thanks.
Devlin
.
- Prev by Date: Re: Multi-drop network
- Next by Date: re:ADPCM Coder/Decoder
- Previous by thread: Re: Multi-drop network
- Next by thread: QRY regarding IOP80331
- Index(es):
Relevant Pages
|
