Re: Help Determining Machine Cycles

From: Jim Stewart <jstewart@xxxxxxxxxxx>
Date: Tue, 31 Jan 2006 12:51:14 -0800

Adam Elbirt wrote:

True but there must be some way to say something to the effect of "a register to register XOR instruction requires NNN machine cycles" as a basic thing for each machine. Does that make sense?


I'm not sure.

If the execution time of a given instruction
is dependant upon whether or not the opcode
and/or the data is in the L1 cache, the L2
cache, or had been executed out of order,
a machine cycle count doesn't mean anything
because it will be different depending on all
these things.

Maybe someone else with a little more insight
could chime in...

Jim Stewart wrote:
Adam Elbirt wrote:
Anyone know where there might be a table similar to what is shown at http://fux0r.phathookups.com/programming-tutorials/Assembly/opcode.html to determine the number of machine cycles for a given assembly language instruction for Intel processors newer than the regular Pentium? I'm interested in Pentium II, III, Pro, etc.
I'm not sure such a table would mean much,
what with 2 levels of cache and pipelining,
out-of-order execution, etc...

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Re: Help Determining Machine Cycles
... register to register XOR instruction requires NNN machine cycles" as a ... is dependant upon whether or not the opcode ... and/or the data is in the L1 cache, ...
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Re: Help Determining Machine Cycles
... True but there must be some way to say something to the effect of "a register to register XOR instruction requires NNN machine cycles" as a basic thing for each machine. ... http://fux0r.phathookups.com/programming-tutorials/Assembly/opcode.html to determine the number of machine cycles for a given assembly language instruction for Intel processors newer than the regular Pentium? ... what with 2 levels of cache and pipelining, ...
(comp.arch.embedded)