Re: Help Determining Machine Cycles

"Jim Stewart" <jstewart@xxxxxxxxxxx> wrote in message
news:cImdnWWv84FeUELenZ2dnUVZ_sOdnZ2d@xxxxxxxxxxxxx
> Adam Elbirt wrote:
>
> > True but there must be some way to say something to the effect of "a
> > register to register XOR instruction requires NNN machine cycles" as a
> > basic thing for each machine. Does that make sense?
>
> I'm not sure.
>
> If the execution time of a given instruction
> is dependant upon whether or not the opcode
> and/or the data is in the L1 cache, the L2
> cache, or had been executed out of order,
> a machine cycle count doesn't mean anything
> because it will be different depending on all
> these things.
>
> Maybe someone else with a little more insight
> could chime in...
>

I don't know where such a table is but I would start with the chip docs ;-)

As to how valuable it would be: The only reason for counting cycles is to
estimate the time required for some tight, assy coded loop. In that case,
you can assume that after the first time through, the loop code is entirely
in the on-chip cache (not counting external events like interrupts). The
same can be true of data IF the loop indexes linearly. That is, the SDRAM
burst fills the cache most of the time so maybe 9x% cache hits.

Now, when you get to out of order execution, you're on your own. When I
write tight loop code like that, I tell the assembler exactly *which*
instructions are allowed to execute in parallel ;-)

Bob

>
> >
> > Jim Stewart wrote:
> >
> >> Adam Elbirt wrote:
> >>
> >>> Anyone know where there might be a table similar to what is shown at
> >>>
http://fux0r.phathookups.com/programming-tutorials/Assembly/opcode.html
> >>> to determine the number of machine cycles for a given assembly
> >>> language instruction for Intel processors newer than the regular
> >>> Pentium? I'm interested in Pentium II, III, Pro, etc.
> >>
> >>
> >>
> >> I'm not sure such a table would mean much,
> >> what with 2 levels of cache and pipelining,
> >> out-of-order execution, etc...
> >>
> >>


.

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