Re: TL16C550CIFN

In article <1139283451.518058.196470@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>,
wuyi316904@xxxxxxxxx says...

CBFalconer wrote:
"wuyi316904@xxxxxxxxx" wrote:
CBFalconer =E5=86=99=E9=81=93=EF=BC=9A
"wuyi316904@xxxxxxxxx" wrote:

Thanks a lot,I have a problem that I have set a simulation model to
verify this UART's DMA function,but the /RXRDY goes true when there is
only one character in the rxbuffer(I set the trigger level is 14),I
want to know why and can u give me a example of DMA mode configuratio=
n=2E

... snip about context. You caught on ...

IIRC most cacheing UARTs will allow you to adjust the trigger point
(items in the cache) at which an interrupt will be raised. The
RXRDY signal has a different purpose, it simply signals that that
cache is non-empty. Thus once an interrupt occurs the service can
be of the general form:

while (rxrdy) buffer[index++] =3D rxdata;
/* now reset and rearm interrupt system */

Thus avoiding the overhead of a system interrupt for each byte.

I don't know ur meanings very much. My problem is that the /RXRDY
does't operate correctly, it gose true(low) when the first byte has
received by the rxbuffer, not when the rxbuffer reach the trigger.

And I pointed out that it is correct. The trigger controls the
point at which an interrupt is raised. This has nothing to do with
DMA. It has everything to do with interrupt service. Data rates
from UARTs will normally be much too slow to bother with DMA
operation.


Are you aware that almost all uarts with FIFOS raise the interrupt not
only when the trigger point is reached, but also when there are one
or more characters in the FIFO and more than three (or so) character
times pass with no new characters? This is to help you make sure
that you don't wait forever at the (trigger level-1)th character.


Mark Borgerson

.

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