Re: Memory map?
- From: "Tom Lucas" <news@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Fri, 28 Apr 2006 17:11:32 +0100
"Fizzy" <fpgalearner@xxxxxxxxx> wrote in message
news:1146236764.517924.301860@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi,
What is memory mapping. If i memory mapped registers in my pheipheral,.
The value written to them is teh value written to memory or it will be
written on physical registers in Pheripheral. Let me explain you cauz i
know my description is bit confusing.....
I'm not sure I completely understand your problem but I know what a memory
map is and perhaps that will help you.
Suppose we have a processor with a 16bit address bus and an 8 bit data bus.
This means you can directly address 2^16 locations - 65536 (10000hex) and
therefore you can have a maximum of 64K of memory. Now let's say you have 8K
of RAM and 8K of ROM. You would like to have it so that the first 8K memory
location are RAM and the next 8K are ROM. You will need address decode logic
to do this (in this case the top address bit connected to both device's chip
selects will do).
This means your memory map will look like this (using hexadecimal numbers):
0000 ------------
RAM
7FFF------------
8000-------------
ROM
FFFF-------------
Now it doesn't have to be memory devices that you use - peripherals will
work just as well. You could have a UART with 16 directly addressable
registers. You could position it after the RAM and before the ROM (but it
would mean 16 locations of ROM have to be sacrificed because you can only
address 64K overall).
0000 ------------
RAM
7FFF------------
8000-------------
UART
800F-------------
8010-------------
ROM
FFFF-------------
The UART does not know that it's address actually begins at 0x8000 - you
will be required to have some logic which looks at the requested address on
the address bus and decides that that address falls within the range of the
UART and so the appropriate control signals to the UART should be asserted
to access it. This is made simpler in an FPGA because you have plenty of
logic available to do this.
I have FPGA with a processor. Now i want to connect this processor with
Custom IP (on FPGA) using Processor Local Bus. I know custom IP has
bunch of registers which will recive the data and send the data. These
register i will create and to my understanding they are in pheripheral.
My question is ......
Are these registers really physically there or they are just the map.
SO when Processor will want to write to one of them it will write to
the memory and Pheripheral will knwo something is written to it?
I'm not sure but I think your problem is in directing the processor to your
registers. The processor will have its own idea of how it's memory map is
laid out and you need to fit in around that. If, when you run your program
and it wants to read from one of your custom IP registers, you need to make
sure that your address decode logic provides that register's contents on the
data bus when this address is requested. How that happens is up to you but
if you put some thought into where in the processor's addressable memory
space you want it to be it should be some fairly simple logic expression.
I'm not sure about what you mean with "Are these registers really physically
there or they are just the map" but I think that they must be physically
there but you get to them by accessing their place in the map. I.E. on my
processor the first location in flash is at 0x44000000. If I read from that
then the address decode logic knows I want to access flash and will wiggle
the appropriate lines to get the flash to return its first word of data
(address 0x00000000 according to the flash).
.
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- From: Fizzy
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