Re: Two Ethernet MACs in a new DualCore ARM Microcontroller


Same goes for the AT91RM3400.
Boot ROM, copy to internal 96 kB SRAM.
No external bus. loads of serial ports, timers, USB etc.
Can't say that is not a micro.

You are both right; what it needs is a qualifier that defines
the TYPE of Code memory :
Thus we have FLASH uC / ROMless uC ( or FLASHless uC ),
or RAMloaded uC, or ROM uC etc.

RAMloaded uC ( and the DSPs that are calling themselves DSCs )
are becomming more common, and Boot from serial memory has rather
less design impact than a 32 bit SDRAM bus.

One reason is the poor flash speeds, another is the higher
process cost of FLASH, but OnChip RAM for CODE is a valid uC design
choice.

Once the CODE fetch at runtime goes (mostly) OFF-CHIP, that's
when it shifts => Microprocessor, as then the CODE memory is defined
not by the ChipVendor, but by the users design choice.


Then the 8031 is not a microcontroller.
Any set of rules needs to work so that chips generally accepted as
microcontroller
are shown to be microcontrollers if the rules are applied to their
definition.

About here is also when the PCB layers hike, and the EMC testing
from all those BUS CODE fetches, become an issue....

-jg

--
Best Regards,
Ulf Samuelsson
ulf@xxxxxxxxxxxxx
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB


.

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