Re: Caches in embedded systems

On Thu, 04 May 2006 11:14:01 +0300, Paul Keinanen wrote:

On 3 May 2006 18:04:17 -0700, "shrey" <shreyas76@xxxxxxxxx> wrote:

I know caches are avoided in real time applications

Unless the cache is very badly implemented, the worst case timing
occurs when the cache is disabled.

Independent of your cache implementation, the software *can*
cause really bad timing in some cases, especially for data accesses.
When the software hits in (almost) random access patterns a large amount
of memory, i.e. larger than the cache size, each access causes a cache
line load, instead of reading a single word needed by your program. When
that data word is also changed it will furthermore mean that a whole
updated cache line must be written back to memory when a new access is
done.
Of course this behaviour will not happen in general, but it can
happen.
Instruction cache behaviour in general will be good, unless your
compiler is really broken.

Rob
.

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