Re: Caches in embedded systems
- From: Paul Keinanen <keinanen@xxxxxx>
- Date: Fri, 05 May 2006 12:53:32 +0300
On Thu, 04 May 2006 22:21:58 +0200, Rob Windgassen
On Thu, 04 May 2006 11:14:01 +0300, Paul Keinanen wrote:
On 3 May 2006 18:04:17 -0700, "shrey" <shreyas76@xxxxxxxxx> wrote:
I know caches are avoided in real time applications
Unless the cache is very badly implemented, the worst case timing
occurs when the cache is disabled.
Independent of your cache implementation, the software *can*
cause really bad timing in some cases, especially for data accesses.
When the software hits in (almost) random access patterns a large amount
of memory, i.e. larger than the cache size, each access causes a cache
line load, instead of reading a single word needed by your program.
Even in this situation, the difference is not usually that dramatic.
E.g. in a typical x86 implementation with 32 byte cache line and 8
byte (64 bit) wide DRAMs, a cache line loading requires one full
RAS/CAS cycle (which includes the DRAM access time) to get the first 8
bytes and additional three CAS cycles (to get the remaining 24 bytes),
which essentially activates a data selector on the DRAM.
A direct random memory access would still require the full RAS/CAS
cycle to get up to 8 bytes of data. Both the cache line load as well
as the random access read contains a single memory cell access time
(which depends on the cell technology), while the cache load
additionally multiplexes three times 8 bytes on the memory data bus
(the time depends on the bus speed).
that data word is also changed it will furthermore mean that a whole
updated cache line must be written back to memory when a new access is
The need for immediate write back usually occurs in direct mapping
caches, but in any associative mapping, the write back can usually be
It should be noted that with direct access, a read and a write cycle
must still be performed.
Even a single byte write to a 2 .. 8 byte wide memory will require a
read operation to get the unmodified bytes from the memory word, then
replace the byte to modified in the CPU and then write back the full 2
... 8 byte wide memory word, unless of course you have up to 8 separate
write enable signals for each byte.
The difference between direct access and cached access is not that
great as it might first appear.
Of course this behaviour will not happen in general, but it can
In hard real time systems with firm deadlines the worst case situation
must still be identified.