Re: 8051 architecture

Chris Hills wrote:
In article <1152649623.527310.218010@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>,
Isaac Bosompem <x86asm@xxxxxxxxx> writes
eerobert@xxxxxxxxx wrote:
Why 8051 need 2 clock cycle for 1 system state?
I do not know what you mean by "system state". I only know that the
8051 by default takes 12 cycles for a machine state (I think that is
what you meant).

The original 8051 took 12 cycles.

There are many 8051 cores that use one of 12, 6, 4, 2 and 1 cycle per
clock.

There are some 30-40 different cores out there using different internal
design philosophies from traditional to soft cores fro ASICs. This means
their internal timing is different.

Some do run in 2 clock cycles per machine state.



When I started with all this microprocessor malarkey, life seemed to be full of low-level machine architecture with much talk of things like fetch-execute cycles. By and large, many folk seem not to either want or need to know about these things, especially if all their development is done in a high level language. Not long ago I was sharing a moaning session with a university lecturer about how electronics students don't seem to have to know much at all about semiconductor junctions in order to get a degree. But I digress..

The OP asked a question that we must assume had some meaning and relevance to him. Granted, it was poorly phrased and possibly ambiguous. However, almost nobody seems to have tried answering the question and most seem to have almost willfully misinterpreted it. the original question asks about the need for 2 clocks per machine state in the 8051. A quick look at the Philips databook to remind me what an 8051 was (just kidding - stay calm) shows that a machine cycle consists of six machine states, each requiring 2 clocks. So all this stuff about 1, 2, 4, 6 and 12 clock variants is a bit beside the point. If the OP really meant machine state (as written) rather than machine cycle (as read by most) then the question is probably quite fair. Certainly, a look at the Philips databook makes things a bit more clear. There is a small section specifically about CPU timing and Machine cycles. However, the family hardware guides most likely to be found by a less than thorough Google search don't always mention it. The 80C51 Family Architecture document found here:

http://www.semiconductors.philips.com/acrobat_download/various/80C51_FAM_ARCH_1.pdf

says what there is to say I think although it still falls short of explaining why two oscillator periods are required for each machine state.

Sadly the most succinct answer posted so far is just as unhelpful - it was designed that way. All the actions appear to take place on the falling edge of the oscillator clock. using both edges would have taken a single clock per state but was presumably an expensive complication at the time the original 8051 was designed.


Of course, the OP could have simply dropped a 1 and meant why 12 clocks per machine cycle - who knows. We will never find out because he has probably been securely frightened away and should not cause any more embarrassment to himself or others.

Pete Harrison
.

Relevant Pages

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