Re: 8051 architecture

Peter Harrison wrote:


The OP asked a question that we must assume had some meaning and relevance to him. Granted, it was poorly phrased and possibly ambiguous. However, almost nobody seems to have tried answering the question and most seem to have almost willfully misinterpreted it. the original question asks about the need for 2 clocks per machine state in the 8051. A quick look at the Philips databook to remind me what an 8051 was (just kidding - stay calm) shows that a machine cycle consists of six machine states, each requiring 2 clocks. So all this stuff about 1, 2, 4, 6 and 12 clock variants is a bit beside the point. If the OP really meant machine state (as written) rather than machine cycle (as read by most) then the question is probably quite fair. Certainly, a look at the Philips databook makes things a bit more clear. There is a small section specifically about CPU timing and Machine cycles. However, the family hardware guides most likely to be found by a less than thorough Google search don't always mention it. The 80C51 Family Architecture document found here:

http://www.semiconductors.philips.com/acrobat_download/various/80C51_FAM_ARCH_1.pdf


I guess the reason is the way the first generation of 8051 is designed.
(there wasn't VHDL/Verilog at that time, the chip layout was manually
created).

At that time, registers could be implemented as latches.
So the first 8051 might have used "register" design that
required multiple clock phases to drive. For example,
1 flip-flop = 2 multiplexer latches in series
As a result, 2 clock cycles might be required to ensure correct
operation of the register.
And the design use 2 clock cycles for each machine state.

Joseph



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