A strange thing
I am a newer for FPGA. I implemented one algorithm into FPGA board. I
sent data generated by Matlab from PC to FPGA board. And the results
are sent back to Matlab. Becuause I need caculate the bit error rate, I
tried it many times. I set the number of trials is 10000. It did work
in some trials at first but stopped at some trial. The Matlab always
show busy but not continue to next trial. I have to close Matlab and
try again. The phenomenon happens every time. Is this the problem of my
vhdl codes？ But how can it successuflly work for some trials (even
reached 9883 trial)? Has anybody seen the thing before ? Or just give
me some suggestions. Thanks.
.
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