Re: SI and EMI training

rickman wrote:
PeteS wrote:
I, like a number of others here, have done highspeed designs (my upper
limit on copper is currently 5Gb/s) and although there is sufficient
theory to calculate the number of bypass caps, in practice there are
usually insufficent time and tools to use all of it.

A reason we have rules of thumb is that they usually work. Usually, of
course, is a key word here ;)

Yes, the instructor mentioned this many, many times, ususally followed
by the statement, "If you don't have time to do it right, do you have
time to do it again?" He also had many examples of companies that
called him in to solve a problem and he had to tell them to do it over.
Some of those companies had blown their VC money and were not able to
do a redesign.


Others could no doubt give you a real design, but here's one to chew
on:

Consider doing a board with said 5Gb/s pairs (but make sure there are
almost 400 such pairs) on a 16 layer board [constrained to that because
of drill sizes available for breakout], where the devices with those
signals require 4 different power supplies (an entire EMC/EMI issue in
itself) and a backplane (or perhaps a cable) connector.
Once you have figured out your routing (autorouters are worse than
useless with these types of signals) and your via strategy (taking a
signal of this speed through the board requires special care), you
might find that there are so many variables that you simply sprinkle a
few (make that dozens or even hundreds) extra caps into the thing.

He gave us examples with multiple high speed signals and he still used
the same methods. One had 17 different power supplies and most had
connectors in the high speed signal path. So I don't see where a
complex board makes "rules of thumb" more important, but rather less
important. The problem with a general rule is that it has to be
qualified and no one remembers the qualifications.

I think that these sorts of general rules are used not because it is
not important to know how to do it right, but because people don' t
know how to do it right. I am always happy to learn how to replace a
"voodoo" rule with a knowledge based rule.


This all ignores the other various control and status in the device
(things like DDR memory and processors - you get the picture).

Actually he used memory interfaces in his examples and even spoke of
how DDR2 is not currently working. Heck, I remember that from SDRAM.
They were making motherboards with it, but you frequently could not
populate all the slots or it would only work with certain brands of
memory which differed between brands of motherboards. This was an SI
issue. With DDR2 it seems that the problem is just too tough to solve
so they are going a new version which will buffer the signal on each
DIMM and daisy chain the signal path.


You might not populate them, but the positions are there for insurance,
as are a bunch of ferrites and resistors. Considering we can fit
literally hundreds of discretes in a square inch and they typically
cost less than 10/cent in the quantities we buy in, such insurance is
cheap.

I hear that a lot. Sure caps are cheap, but board space is not,
especially on high layer count boards. Don't forget that every cap
needs two vias which create routing congestion on all layers. The
design methods he used don't take a lot of time, you just have to do
them.


Yes, it is interesting to see what the required decoupling is (and
that's only part of a complete EMC strategy), but in practice there
will always be some unknowns that there is *no time to solve* of you
are ever going to ship your product.

Can you give an example of some of these unknowns?


It might be intellectually satisfying to know one has done the minimum
required to get EMC at an acceptable level, but EMC is one of those
areas where apparently innoccuous things can bite you.

I had a device (one of the x-point switches in the above design as it
happens) that was flip-chip and had a hefty heat sink. The heat sink
fins *just happened* to be 1/4 wavelength and operated as pretty damn
fine antennae on the unavoidable differential to common mode converted
signals in the area. That has little to do with decoupling, but extra
decoupling of the device helped minimise the *internal* common mode
conversion. I also had to find a different heatsink (not easy as I
needed to dissipate lots of heat, but the enclosure limited the height
of the heatsink) and adjust the forced air cooling.

So bear in mind that there are really good reasons we sprinkle
decoupling liberally on designs ;)

I'm not clear on how the decoupling caps helped here. I'm not familiar
with the term "*internal* common mode conversion". If your power plane
is well designed there will be very little noise to radiate. He did
mention that to create EMI you needed two things; noise and an antenna.
Signals on the board are not good antennas, so they don't radiate
much. Your heat sink sounded like a perfect radiator at a critical
frequency. You changed the heat sink, so how did the caps help?

I'm not trying to change everyone's methods of designing. But this
class changed a lot of my thinking where I had been using these
"voodoo" rules. Partly I am posting to inform others that these rules
are not good or necessary and partly I am posting to find out what
others are doing. You seem to be a designer who is happy using "rules
of thumb". If you are interested, you might consider buying Ritchey's
book, "Right the First Time, a Practical Handbook on High Speed PCB and
System Design". I don't recall how much the class was, but I would
certainly recommend it.

So many things :)

First, I do not apply rules of thumb blindly - I use a systematic
approach to EMC/EMI and indeed all parts of my design. So covering a
few things:

1. I try to follow the device manufacturer's exhortations on
decoupling, although in my experience they specify far more than is
truly necessary (as no doubt your instructor mentioned), but as I am
not privy to the internal layout of the device, putting fewer devices
on for decoupling is a risk I must weigh. There are many times I have
indeed put fewer decouplers on a board than the chip mfr specified. I
have the PeteS[tm] decoupling analysis tool (it actually is a
spreadsheet) that I use.

2. Signal integrity consists primarily of maintaining the signal and
preventing it from radiating. In the case of differential signals, this
includes preventing differential mode to common mode conversions. As
Howard W. Johnson says 'perfectly matched lines don't radiate'.
Incidentally, I have a copy of his book 'High speed digital design. A
handbook of black magic' on my shelf.

To answer a question: Internal common mode conversions on CML type
drivers occurs for a number of reasons, but one of them is because the
transistors are not a perfect match, there is *some* transient current
during switching from one state to the other. Better decoupling reduces
this effect. I use the term internal here to mean internal to a chip,
not due to track mismatch (impedance or length). In this case, it
converts to a common mode signal *on the power supply rail* which is
why extra decoupling helps.

3. I am sure the course you did has great value, and indeed I am glad
to see people doing such courses; at least you are now aware of the
fact that thre is more to SI and EMC than simple decoupling. I am also
certain your instructor is highly knowledgeable in the subject. He, of
all people, would proably accept that 'nobody knows it all' and that
some techniques practised by the unwashed masses may indeed have value.

4. Even on high density boards, I can always find room for a few extra
decouplers (although maybe not what the mfr wants - see above). I have
done boards with an average density of >150 pins/sq. inch and still
managed to get a few extra caps on there - it also passed EMC testing
by design (although I admit to thinking myself lucky) and had a 14dB
margin at that.

5. When designing a system, you have to accept that you *manage* EMI
because you can not eliminate it.

As I now have to fix dinner, I'll have to stop for now. More later
perhaps :)

Cheers

PeteS

.

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