Re: SPI Bus Specification

Wulf wrote:
On 5 Sep 2006 09:51:42 -0700, "rickman" <gnuarm@xxxxxxxxx> wrote:

I searched this group and could not find much on an actual spec for the
SPI bus. I know that this bus is very loose. One of my coworkers
refers to it as a non-standard standard. But I will be doing some
strange things to a couple of SPI bus interfaces to pass them through a
cable using fewer pins than otherwise required and the relative timing
will be delayed by up to a uS or so. The bus will be running with a
101 kHz clock so I expect this will work, but I wanted to find some
timing data on the bus.

I did find a Freescale doc that shows the clock phasing an polarity,
but no timing requirements. I guess it is up to the engineer to verify
the low level timing of the various devices on the bus?

I could not find anything on timing at the Freescale site.


The SPI is relatively easy. I've done several. Both bit-banged out and
hardware dedicated on uP's . Just check your timing diagrams for both
the source and destination. I've always used the CPU as master. Also,
make sure to not violate any setup and hold times as well. At 100kHz
it should be a breeze :) .

Ay, there's the rub! I don't have info on the source or destination.
I am just a middle man. But with a 100 kHz bus clock, I am pretty
confident that this will work. Someone cautioned me that if the jitter
swaps the edges of clock and data it could be a problem. But I think
this is not true unless you cause an edge to move a half clock cycle.
I don't see how it can matter if the data changes slightly before the
active edge of the clock (instead of after) since the active edge for
the receiver is the other edge.


If you want more information you will have to provide details on what
you are talking about as far as "fewer pins", SPI doesn't have that
many pins.

I am not asking for help with the logical design. I am looking for
timing information so I can determine how much slack there is in the
system I am working with. Obviously there is no bus level spec on the
timing. Rather it is up to each designer to assure that his use of
different devices is compatible.

.

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