Re: Generating 6MHz output frequency

djordj wrote:

I need to drive a 320x240x8bbp TFT color display (Hitachi XT14 series).
I need to provide a clock signal @ ~6MHz and I can't use a micro with a built in controller.

Options are:
1) driving the TFT directly from the microcontroller
2) using an EPSON controller (or a dedicate FPGA)

As I have to use STR9 chip, I'm trying to figure out if I can really obtain this output frequency: the problem is that the micro PLL can raise the internal clock frequency upto 96MHz.
At first look, I might have to invoke a sort of IRQ @ 12MHz to drive the output pin HIGH-LOW with 50% duty-cycle: may I use a timer output compare interrupt, but here comes the trouble.

12Mhz means Toutput = 83.3nsec
96Mhz means Tclock = 10.4nsec

So I have just 8 clock cycles between two consecutive IRQs.
Considering that I have to get pixel value from DRAM, decode it to RGB palette and the put it on the output pins..... (not to speak about the needed IRQ control overhead).

This morning I've begun to look at EPSON / FPGA controller :P

Points are:
0) can STR9 pins be swapped HIGH to LOW at 6Mhz @96MHz clock?
1) is there any tricky solution?
2) Is there some VHDL code ready to drive a TFT display: I've got short time to market and I can't afford a FPGA development.
3) any other suggestion will be very appreciated

Thanks!

You do not want to do this in an IRQ.
Where does the STR9 get the ref for the 96MHz PLL ?
Commonly you would have a 6 or 12Mhz Xtal Osc module, and then
PLL that up to the 96MHz, ie you just choose your initial XTAL
so it is easy to get 6MHz from it.

If there are other complexities, I'd also look at a small CPLD,
which can handle the MHz region clocks very easily, and
re-frame the datastreams into something the uC can manage.

-jg




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