Re: non load/store architecture?


David Brown wrote:

Where does that leave us? A pure RISC architecture is best when aiming
for maximal ipc, and can be run at higher clock speeds as each step is
simpler. But the ColdFire code is more compact, leading to lower
bandwidth requirements on the instruction bus, and it does more per
instruction, giving better performance for the same ipc.

Working on OpenGL device driver optimization for the DEC Alpha, I never
saw instruction cache misses. Only data cache. Performance code is in
small loops, not huge hulking one-shots. I say "more compact code
improves performance" is theory, and not observable in practice. More
compact data, on the other hand, matters a great deal.

Being low power is a good indicator of an efficient ISA - the x86 is not
low power, and neither are most fast RISC cores as they need high clock
speeds. Remember, what's important for a processor is the work done per
clock, not just instructions per clock, and in comparison to a pure RISC
architecture, the ColdFire sacrifices a little ipc for a lot more work
done per instruction.

The units of work I've always cared about are FPU adds, multiplies, and
divides. There isn't more arithmetic work to do per instruction. You
could do more load/store work, but assuming you hit your primary data
cache, that's not your bottleneck anyways. The arithmetic is. As I
said above, instruction cache bloat doesn't matter in tightly looping
code. Or, I'd wager, in loosely looping code either. Instruction
caches are pretty big compared to the looping code. If all your code
is one-shot then you've got completely different system caching issues,
nothing to do with the CPU.

Now I suppose if you design CPUs with almost no cache, you might care
about instructions being small. But then, you're not designing a
performance CPU anyways. So who's gonna care about the performance?
"Good" won't mean optimization, it'll mean low power or cheap to
manufacture or something.


Cheers,
Brandon Van Every

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Relevant Pages

  • Re: non load/store architecture?
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  • Re: non load/store architecture?
    ... (See what I mean about ColdFire code being nice and clear?) ... the same clock. ... acceptable to do an "instruction dance," that doesn't typically run ... and also your code cache alignment. ...
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