Good document on ARM cache policies w.r.t. timing?

Once I finish preparing the materials, I'm giving a short lunchtime
presentation at work about estimating CPU loading and latency.

I'd like to add some discussion about the difficulty of doing a simple
count-the-cycles analysis on multi-cached, pipelined RISC
architectures, where things start to get nondeterministic. I'm
particularly keen to describe how this might affect ARM7[xxx] and ARM9
designs, because a lot of teams here are starting to migrate 8051 and
other 8-bit designs into ARM micros.

I don't mind groveling through the ARM ARM and working it out from
first principles if I have to, but is there a reference that already
discusses these issues? For instance, if you're running with the MMU in
full swing, L1 and L2 page tables in use, can you lock your ISR's table
entries in the TLBs so the MMU doesn't have to touch RAM to look them
up? How to lock code into cache? Is a cache line fill aligned on a hard
memory boundary or will it fill from an arbitrary starting address,
based on where you just touched memory?

.

Relevant Pages

  • Re: Good document on ARM cache policies w.r.t. timing?
    ... I don't mind groveling through the ARM ARM and working it out from ... How to lock code into cache? ... Is a cache line fill aligned on a hard ... I somewhere had a document going into this in some detail and a doc from Broadcom looking at it for the parts I used (MIPS core based) because it impacted the internal bus significantly. ...
    (comp.arch.embedded)
  • Re: Embedded linux: With or without MMU
    ... Remember, ARM was originally designed for desktop use as well, AFAIK .. ... The first ARM was for the Acorn Archimedes machines, but it did not have an MMU, and I'm not sure that it even had a cache. ... There are two ways to handle cache and MMU - you can cache by physical address (which causes slower access to the cached data, as addresses need to be translated before accessing the cache), or you can cache by virtual address. ...
    (comp.os.linux.embedded)
  • Re: Embedded linux: With or without MMU
    ... task switch the OS has to do some work to reprogram the MMU (and with ARM the cache gets invalidated). ... Remember, ARM was originally designed for desktop use as well, AFAIK .. ...
    (comp.os.linux.embedded)
  • Re: ARM9 boot up
    ... have you even bothered to read the ARM ARM? ... MMU off at POR => cache off at POR. ...
    (comp.arch.embedded)
  • Re: Exploring Windows CE Shellcode
    ... > well xscale to be exact but thats arm v5 IIRC. ... > similar problems in your WinCE shellcode? ... Tim is flushing the cache using the following instruction: ...
    (Pen-Test)