Re: Good document on ARM cache policies w.r.t. timing?

larwe wrote:
Once I finish preparing the materials, I'm giving a short lunchtime
presentation at work about estimating CPU loading and latency.

I'd like to add some discussion about the difficulty of doing a simple
count-the-cycles analysis on multi-cached, pipelined RISC
architectures, where things start to get nondeterministic. I'm
particularly keen to describe how this might affect ARM7[xxx] and ARM9
designs, because a lot of teams here are starting to migrate 8051 and
other 8-bit designs into ARM micros.

I don't mind groveling through the ARM ARM and working it out from
first principles if I have to, but is there a reference that already
discusses these issues? For instance, if you're running with the MMU in
full swing, L1 and L2 page tables in use, can you lock your ISR's table
entries in the TLBs so the MMU doesn't have to touch RAM to look them
up? How to lock code into cache? Is a cache line fill aligned on a hard
memory boundary or will it fill from an arbitrary starting address,
based on where you just touched memory?


I somewhere had a document going into this (done at Stanford IIRC) in some detail and a doc from Broadcom looking at it for the parts I used (MIPS core based) because it impacted the internal bus significantly.

Even though it's MIPS based, the basic issues would be the same, one might think.

I'll dig around and see if I can find them.

Cheers

PeteS

.

Relevant Pages

  • Good document on ARM cache policies w.r.t. timing?
    ... I don't mind groveling through the ARM ARM and working it out from ... entries in the TLBs so the MMU doesn't have to touch RAM to look them ... How to lock code into cache? ... Is a cache line fill aligned on a hard ...
    (comp.arch.embedded)
  • Re: Exploring Windows CE Shellcode
    ... > well xscale to be exact but thats arm v5 IIRC. ... > similar problems in your WinCE shellcode? ... Tim is flushing the cache using the following instruction: ...
    (Pen-Test)
  • Re: [PATCH 1/2] DMA buffer alignment annotations
    ... platforms that do not have coherent caches. ... as ARM, MIPS, etc... ... To get this macro, architectures have ... +share a cache line with any other data. ...
    (Linux-Kernel)
  • Re: Locking data and instruction cachelines
    ... I'm using an Intel PXA270 based ARM variant, and I noticed that the article about locking cache lines on ARM's web site seemed to indicate that one can only lock instruction cache lines on ...
    (comp.sys.arm)
  • Generating a Wrap transfer
    ... I wish to implement an ARM wrap transfer as part of SoC Verification. ... am using an ARM926EJ-S as the ARM processor. ... cache line and this is how I could generate a wrap transfer. ...
    (comp.sys.arm)