Re: PIC vs ARM assembler (no flamewar please)

Even a few KB of SRAM is much slower than a register file.

Slower, yes. ....

Generally true, but there are exceptions. TIs 54xx DSPs have some
registers memory adressable (not all, e.g. not the accumulators,
just the so called "auxilary registers"). Whether they are really
memory addresses or not I don't know, the RAM is on-chip at address
0 (about where these register are), and this RAM allows 2 accesses
per cycle, so there is no slowdown out of that. But given that
this architecture allows 3 RAM accesses per cycle (or was it 4?),
this is hardly surprising, it is designed to not have a memory
bottleneck.

Dimiter

On Feb 21, 1:00 am, Jim Granville <no.s...@xxxxxxxxxxxxxxxxxxxxxx>
wrote:
Wilco Dijkstra wrote:
"Jim Granville" <no.s...@xxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:45db4806$1@xxxxxxxxxxxxxxx

rickman wrote:

The TMS9900 used a pointer register (that's right, registers did not
go away) to point to the first register in memory. An ADD would then
take three memory accesses to complete rather than one clock cycle.
Even if you put the memory on chip, you either have to limit the
location of the registers to a special bank of fast, multiport memory
(register bank) or you have to accept multiple memory cycles for a
single instruction, even when working in registers.

Sounds like a poor example of how anyone would do this today.

Look at the XC166, and eZ8, for examples of how you can do
very efficent memory overlays.

In a uC, you are talking of a few K's of memory, so speed should
not be an issue at all.

These are not examples of a RAM mapped register file, just of a
hardware assisted context switch. So the contents of the RAM are
copied to/from the register file but are not kept in sync until the next
context switch.

Which are not ? - perhaps you are talking about the TMS9900 ?

If you meant the eZ8, then perhaps reading up on the Register Pointer
operation would assist. In the eZ8, the register pointer adds to the
4 bit register operand, to map/overlay those 16 registers, into up to 12
bits of RAM



Even a few KB of SRAM is much slower than a register file.

Slower, yes. 'Much slower' is moot - given that the bottle neck in
most CPUs/uC is code access from FLASH, and that on-chip SRAM speeds
are MUCH FASTER than Flash speeds, so it's not looking like the
determining-speed path.

There seems to be no practical speed impact from this, when you
look at the Mhz speeds of real devices like the St10/XC166 cores ?

-jg


.

Relevant Pages

  • Re: can somebody help me with the problem with tasm models
    ... When Intel created the x86 originally, ... registers...now, when addressing memory with something like "", this ... valid...the rest aren't yet wired in and are ignored in memory addressing ... "offset" register, this would give a 20-bit address...if, in time, they ...
    (alt.lang.asm)
  • Re: Calculating checksums...
    ... - it's a word memory reference using a register address ... lods - it's the lods instruction ... parens are a memory reference. ... programming and why, with the end of the 68k, teaching assembly ...
    (alt.lang.asm)
  • Re: Volatile variables
    ... Memory barriers come in four "memory" flavors -- ... one needs only a single "store/load" barrier between the write to ... the command register and the read from the status register. ... does a full CPU pipeline flush and empties the write aggregation ...
    (comp.lang.c)
  • Re: [linux-usb-devel] Re: serious 2.6 bug in USB subsystem?
    ... I'll respond to your concerns about my OHCI changes later on. ... wanted to make progress on the BTC HID issue first so we have the full ... looky here what you get when you interpret the memory at address ... or ControlListFilled bit of the HcCommandStatus register. ...
    (Linux-Kernel)
  • Re: again, external symbols in hla
    ... of a register, then list is the symbolic name of a memory location. ... mov ebx, list ... mov eax, list + 8 ...
    (alt.lang.asm)