Re: PIC vs ARM assembler (no flamewar please)

On Feb 20, 9:53 pm, Jonathan Kirwan <jkir...@xxxxxxxxxxxxxx> wrote:
[snip interesting comments]
But for those making cheap embedded controllers, I suspect that die
size and effectively using somewhat lower FAB technology remains
useful. So the low-transistor count approaches once the much lauded
domain of RISC remain important.

With the note that code density is also a factor. If
the area saved by simpler decoding comes at the cost
of more area in Icache (for the same performance) or
FLASH, then simpler decode is a net loss. Simpler
decoding can also save power, but the reading of
larger instructions consumes more power. RISC also
reduces the design effort required and testing
complexity. At higher volumes design cost becomes
less significant; so the balance point in the
trade-offs between code density and implementation
complexity changes (e.g., per chip design cost savings
can be translated into larger chip area). Per chip
design cost savings can also be translated into a
better (faster and/or more power-efficient and/or
smaller) process technology.

(Greater design effort [whether from ISA factors or
greater effort to optimize the design for power,
performance, and/or area] also increases scheduling
risks; so a sub-optimal ISA or implementation might
be safer. Safer probably means easier access to
start-up capital [a double-whammy because a simpler
design also requires less start-up capital]. Of
course, one also cannot trade costs [number of
designers] for time to completion at a fixed rate.)

It might also be noted that a move to multiple cores
per chip multiplies the decode area savings (but does
not reduce Icache costs) while shared FLASH cost
remains constant.

As you implied, the trade-offs for a real product are
much more complex.


Paul A. Clayton
just a technophile and babbler

.

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