Re: PIC vs ARM assembler (no flamewar please)


"Paul Keinanen" <keinanen@xxxxxx> wrote in message
news:kquku2tajt013lv7nitj84ght90mnckdca@xxxxxxxxxx
On Sat, 03 Mar 2007 23:13:03 GMT, "Wilco Dijkstra"
<Wilco_dot_Dijkstra@xxxxxxxxxxxx> wrote:


"Grant Edwards" <grante@xxxxxxxx> wrote in message
news:12ujjmesqcijscb@xxxxxxxxxxxxxxxxxxxxx
On 2007-03-03, Everett M. Greene <mojaveg@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
wrote:
Grant Edwards <grante@xxxxxxxx> writes:
On 2007-03-03, Robert Adsett <sub2@xxxxxxxxxxxxxxxxxxxxx> wrote:

The classic Harvard architecture has separate instruction and
data buses accessing different memories

At least architectures with different instruction word and data word
length must be harvard architecture. It would be hard to efficiently
put e.g. 14 bit instruction words and 8 data words in the same address
space or even into a unified memory array.

They would likely be Harvard indeed. They could have a unified
address space, for example it would be possible to allow 8-bit and
16-bit reads to a 14-bit instruction memory.

Any other systems with equal addressability granulation in both spaces
but with different logical or physical (memory banks) address spaces
would be on the borderline (harvard or not).

If there are different memory banks and buses to them, then it is a
Harvard. If there is one bus to multiple memories then it is not.

So you're saying it has nothing to do with the number of
address spaces?

Indeed. The original goal was to allow simultaneous access to
both code and data memories. How they fit in the memory map
is a different matter. The early pure Harvards didn't allow data
access to instruction memory at all, but few (if any) of these exist
today.

Why would instruction space data access be required in the early
systems (except for self modifying code, which became more or less
redundant after addition of index registers) ?

You need access to instuction memory to program it. The early
machines were programmed by hand...

Moving data from instruction space to data space has become an issue
with non-volatile data memory and especially in micro controllers, in
which you do not have a program/data loader. The obvious solution
would be to have a data-space initial image in a non-volatile memory
with same word length as the data space. However, this would not be
cost effective, since only a small part of data-memory needs to be
initialised with non-zero values, so a program loader reading with
some special instructions from instruction space would be required.
But after the initial data space loading, there should not be much
need to access the instruction space.

That's not true. A significant proportion of data is const data, and
there is often very little RAM on micro controllers, so copying it from
flash to RAM is simply not an option. Therefore efficient access to
flash is required and flash and SRAM need to share the same
address space. The good thing is that you can still use a Harvard
architecture.

Having 2 or more address spaces doesn't make a CPU a
Harvard. Many CISCs have a separate IO space for example.

Something like a TMS320C4x with a single address space but 3
different physical memory busses is a harvard archicture?

Yes. Most Harvards have a single address space.

That would be quite stupid when one think about bit efficiency. If the
I space is 16 bit wide with word addressing and D-space is 8 bits wide
with byte addressing, 16 bit pointers could access 64 KiW (128 KiB)
I-space and 64 KiB of D-space without any special tricks, such as
segment registers. The need for data access from I-space, so this does
not affect the overall efficiency.

Yes, that is why only a few small 8/16 bitters go for a pure Harvard
architecture - being able to use twice as much memory matters.
But for high level languages a unified memory is the way to go.


Without that
you'd need special instructions to access the different address
spaces (eg. LPM on AVR, MOVC on 8051). Not good for C...

The issue about higher level languages is more the question if the
architecture includes a call stack at all and were it is located
(internal registers/data space RAM) and if it is accessible from the
data space.

You don't need to access the call stack in C, it is perfectly possible
to use separate stacks for data and return addresses. If the hardware
doesn't allow any access to the call stack the only issue is setjmp/
longjmp, but they are not that useful anyway.

Wilco


.

Relevant Pages

  • Fourth edition of Computer Architecture: A Quantitative Approach
    ... Computer Architecture: ... Increased coverage on achieving parallelism with multiprocessors. ... Advanced Techniques for Instruction Delivery and Speculation ... Distributed Shared Memory and Directory-Based Coherence ...
    (comp.arch)
  • Fourth edition of Computer Architecture: A Quantitative Approach
    ... Computer Architecture: ... Increased coverage on achieving parallelism with multiprocessors. ... Advanced Techniques for Instruction Delivery and Speculation ... Distributed Shared Memory and Directory-Based Coherence ...
    (comp.arch)
  • Re: PIC vs ARM assembler (no flamewar please)
    ... multiple busses means "harvard" even thought there's only ... At least architectures with different instruction word and data word ... space or even into a unified memory array. ... byte addressability in the data space would also be a sign of harvard ...
    (comp.arch.embedded)
  • Re: PIC vs ARM assembler (no flamewar please)
    ... Neumann architecture into a Harvard one, ... Historically, there was a match in the number of ports, since Harvard architectures have separate code and data spaces and have two ports, and v.N. ... memory, so are neither pure Harvard nor pure Von Neumann. ...
    (comp.arch.embedded)
  • Re: Learning to use PICS
    ... -If your objective is to understand the architecture of a 16F84, ... It facilitates a uniform instruction set where virtually every ... banking is required in order to access them. ... Not true for the data memory, and mostly no longer true for program memory ...
    (sci.electronics.design)