Re: Atmel releasing FLASH AVR32 ?

The latency for
THREADING INTERRUPT
___________________________________
thread B 2 1 clocks
thread A 1 8 clocks

If you are interested in worst case performance, then the interrupt
structure is 4 times slower in reacting to the event.

Correct, execution of the first instruction is slower indeed. However
this has nothing to do with the maximum frequency of the SPIs...

In both cases the fastest we can receive bits from the SPIs is 2 bits
every 16 cycles. Irrespectively of how many SPIs you emulate, maximum
SPI frequency depends on the total time taken of the interrupt routine.
So clearly the latency of the first instruction does not matter at all.


You dont see how it scales.
If we assume 50/50 duyty cycle on the SPI clock.
The SPI slaves reads on positive edge and the
SPI masters alter data on the negative edge.
Data when SPI clock is low, is to be considered INVALID.

The interrupts occur on the positive edge, and the master must
keep data valid and clock high until the last interrupt has sampled its I/O.

If you have 16 SPIs, then the master cannot release the data until the last
of the
16 interrupt routines has sampled its I/O.

So it can release after (15 * 8) + 1 = 121 clocks forcing total SPI cycle to
be 2 * 121 = 242 cycles.
If we assume that interrupt processing take a number of clock cycles
(12 in case of Cortex) you add 16 * 12 = 192 clocks, to 121 = 313 for half
a period
giving total cycle = 626 cycles.

In the multithreading case, it can release after 16 cycles but is also
limited
by the execution time of each thread so you will have an SPI cycle of 16 * 8
= 128 cycles.

It is really very simple if you open your eyes.



If you have more interrupts, then it can take forever and ever
for the last interrupt to handle it input pin.

Only if higher priority interrupts occur. The interrupt structure is
designed
so that each interrupt can meet its worst-case deadline. This is similar
to
allocating time quanta, but rather than guaranteeing a timeslot that is
fast
enough to handle the worst case, you guarantee the worst case by setting
interrupt priorities. A different methodology, but the end result is the
same.


No it isn't..
Worst case latency for multithreading is in this case 16 clock cycles
and 121 clock cycles for the interrupt case.
Interrupts fall to the ground when you have the same priority.

Also remember that one key function is that multithreading allows two
groups to develop S/W independent of each other and let a third party
use that S/W as a library.
If you run a real time operating systems where the two threads have to
share, then it becomes a mess, which usually results in having two CPUs
instead of two threads.


With the right allocation stucture you can, in a multithreaded CPU
guarantee that you are allocated a certain number of instructions
per time quanta. This is what you need to support worst case performance.

Sure (with time quanta things become more predictable but the latency
goes up too - you can't have both!). However I'm still at a loss as to why
you claim that multithreading would allow for higher frequency SPIs...


Just do the numbers...


Wilco



--
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may not be shared by my employer Atmel Nordic AB


.

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