Re: Serial CPLD

Michael N. Moran wrote:
Spehro Pefhany wrote:

On Thu, 24 May 2007 11:31:04 -0400, the renowned "Michael N. Moran"
<mnmoran@xxxxxxxxxxxxx> wrote:


Thus, we are considering moving that bit-banged serializer logic into a CPLD with an 8-bit bus interface.

The device will need to do things like clock recovery (1KHz), bus arbitration, collision detection, bit stuffing, CRC generation/checking, framing , and bus idle detection, in addition to the RX/TX serial conversions.

Obviously, low cost is a "good thing".


I'm looking for potential part suggestions, with low cost beinig the goal.


Some of the Xilinx Coolrunner II CPLD parts are pretty reasonable and
have plenty of I/O.


If my preliminary calculations are good, then I should
only need about 22 I/O pins including a clock.


Hmmm, 22 I/O = 22 F/F on a small clpd.

One 8-bit output register is 8 FF and one output enable pin, shift register at least 8 FF and a clock input pin, that leaves 4 logic elements for the rest.

Does that about sum it up ??


donald
.

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