- From: "runner" <emb@dded>
- Date: Wed, 13 Jun 2007 14:46:34 +0200
Well, the CMUCam3 http://www.cmucam.org/wiki/Hardware
is not outdated and it deploys one of those Averlogic chips. So
i guess they're in production. The way the FIFO is driven is
more or less what i also planned. The "glue" AND is something
that i wanted to avoid, in case i decide to go on. An input enable
pin (present in some models) should do the trick.
"runner" <emb@dded> wrote in message
- Is AL422B still in production?
- As for Read Operations the datasheet notices:
"When the new data is read, the read address should be
between 128 to 393,247 cycles after the write address,
otherwise the output may not be new data."
Does it mean that data is pushed into the FIFO in 128
bytes sized blocks?
- As for the Single Field Write with Multiple Read Operation:
"In order not to violate the 128 cycles of write to read
delay latency rule, the write address (pointer) needs to
be reset to 0 for the coming multiple read operations so
that FIFO can provide the expectant data at DO bus."
Does it mean that using the chip for single frame captures
is hard ?
- From: runner
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