Re: Address decoding within SOC

joshc wrote:
Within an SOC that has multiple processors connected via AXI buses,
where does the address decoding logic reside? If there are peripherals
like a UART that are shared between the processors, would they have to
be memory mapped at the same address in the address space of both
processors? This is why I am asking where the address decoding logic
resides.

Thanks.


Hi there,

The decoding implementation depends on what type of AXI interconnection
infrastructure you are using. If you are using the ARM PrimeCell AXI
Configurable Interconnect (PL300), then the decoding is done inside the
PL300 itself. For each bus master interface inside PL300, there is an
address decoder. For multiple master system, there are multiple
of these address decoder and they have the same address decoing function.

(See section 2.3 of http://www.arm.com/pdfs/DDI0354B_aci_pl300_r0p1_trm.pdf)

Please notice that peripherals like UART will be more likely to be
put on an APB bus. You can connect an AXI to APB bridge to a PL300
and then attach multiple peripherals to it. For the decoding of multiple APB devices, sometimes a separated APB decoder could be used,
but there is also APB bridge designs that integrated an address decoder.

Regarding what Adrian was looking at, each AXI slave interface has an arbiter (also a part of the PL300).
(See section 2.1.4 of http://www.arm.com/pdfs/DDI0354B_aci_pl300_r0p1_trm.pdf)

regards,
Joseph
.

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