Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics

On Wed, 20 Jun 2007 08:43:06 GMT, "Wilco Dijkstra"
<Wilco_dot_Dijkstra@xxxxxxxxxxxx> wrote:

It now says:

"The disadvantage of a Harvard Architecture microcontroller is that because
instruction and data memory do not share the same PHYSICAL bus, there
can be a reduced level of flexibility in the hardware for some applications."

That's incorrect. All Harvards have a connection between the instruction and
data memories.

The term "Harvard architecture" was actually first coined in order to
distinguish computers using separate memories. Separate memories
have, seemingly by definition to me, separate buses. The use of the
term has evolved somewhat, though, so that some today actually appear
to use the term for architectures which merely use separate caches but
a single memory.

(Memory serving, I think a search for MARK-III and MARK-IV [which used
vacuum tubes] at Harvard would perhaps provide some details on the
origin of the term.)

So I would avoid your choice of "incorrect." Frankly, separate
memories are still in use (PIC, for example, which requires separate
instructions defined to access program space data) and a term for that
is still needed, despite the fact that some attach other meanings to
the word. I'd prefer to suggest a note is added explaining that there
are other uses (single memory, different caches, for example) for the
term and to provide several alternative uses, since practice seems to
have now acquired them.

However, I think Bill was coming from good territory.

Jon
.

Relevant Pages

  • Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics
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