Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics


"Jonathan Kirwan" <jkirwan@xxxxxxxxxxxxxx> wrote in message news:jtti731d8arsncv3khgrkrl2ou6k58gli7@xxxxxxxxxx
On Wed, 20 Jun 2007 08:43:06 GMT, "Wilco Dijkstra"
<Wilco_dot_Dijkstra@xxxxxxxxxxxx> wrote:

It now says:

"The disadvantage of a Harvard Architecture microcontroller is that because
instruction and data memory do not share the same PHYSICAL bus, there
can be a reduced level of flexibility in the hardware for some applications."

That's incorrect. All Harvards have a connection between the instruction and
data memories.

The term "Harvard architecture" was actually first coined in order to
distinguish computers using separate memories. Separate memories
have, seemingly by definition to me, separate buses.

The initial Harvard's did indeed have no connection between memories
because programs were entered by hand. But no such computers are
in existence anymore as such a design doesn't make any sense at all.

The use of the
term has evolved somewhat, though, so that some today actually appear
to use the term for architectures which merely use separate caches but
a single memory.

Exactly, this is what most people mean when they say "Harvard" nowadays.

So I would avoid your choice of "incorrect." Frankly, separate
memories are still in use (PIC, for example, which requires separate
instructions defined to access program space data) and a term for that
is still needed, despite the fact that some attach other meanings to
the word. I'd prefer to suggest a note is added explaining that there
are other uses (single memory, different caches, for example) for the
term and to provide several alternative uses, since practice seems to
have now acquired them.

It's called pure Harvard if the address spaces are separate (again this term
is in widespread use). However in all cases there is a bus that connects both
memories, as you need to read constant data, program the flash, or whatever.
Bill seems to be claiming that Harvard microcontrollers do not have a physical
connection between the memories - that is incorrect whatever definition you use.

Also I don't know what reduced hardware flexibility he is alluding to, but for
pure Harvards there is additional *software* complexity if you want to read from
the instruction memory. As Cortex-M3 is not a pure Harvard, that doesn't apply.

Wilco


.

Relevant Pages

  • Re: PIC vs ARM assembler (no flamewar please)
    ... At least architectures with different instruction word and data word ... length must be harvard architecture. ... They would likely be Harvard indeed. ... 16-bit reads to a 14-bit instruction memory. ...
    (comp.arch.embedded)
  • Re: PIC vs ARM assembler (no flamewar please)
    ... multiple busses means "harvard" even thought there's only ... At least architectures with different instruction word and data word ... space or even into a unified memory array. ... byte addressability in the data space would also be a sign of harvard ...
    (comp.arch.embedded)
  • Re: PIC vs ARM assembler (no flamewar please)
    ... both code and data memories. ... How they fit in the memory map is ... The "Harvard Architecture" I learned about in grad school meant ... dedicated buses. ...
    (comp.arch.embedded)
  • Re: PIC vs ARM assembler (no flamewar please)
    ... both code and data memories. ... The "Harvard Architecture" I learned about in grad school meant ... means multiple physical memory busses -- so a processor with 3 ... Many CISCs have a separate IO space for example. ...
    (comp.arch.embedded)
  • Re: PIC vs ARM assembler (no flamewar please)
    ... multiple busses means "harvard" even thought there's only ... How they fit in the memory map ... access to instruction memory at all, but few of these exist ...
    (comp.arch.embedded)