Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics

On Wed, 20 Jun 2007 08:43:06 GMT, "Wilco Dijkstra"
<Wilco_dot_Dijkstra@xxxxxxxxxxxx> wrote:


"Bill Giovino" <contact1@xxxxxxxxxxxxxxxxxxx> wrote in message news:wPqdnfD32sqW1uXbnZ2dnUVZ_vWtnZ2d@xxxxxxxxxxxxxx

"Simone" wrote...
On 19 Giu, 11:40, Jim Granville wrote:
Bill Giovino wrote:
http://www.microcontroller.com/news/arm_cortex_stm.asp

It now says:

"The disadvantage of a Harvard Architecture microcontroller is that because
instruction and data memory do not share the same PHYSICAL bus, there
can be a reduced level of flexibility in the hardware for some applications."

That's incorrect. All Harvards have a connection between the instruction and
data memories.

Not necessary, unless you use some kind of immediate addressing mode
to load a constant value following the opcode into the data space.

On micro controllers this is a direct physical connection as
you need a way to read constant data from flash.

In a Hardware architecture, there is no requirement that the flash
should reside only in the code space, you could have flash memories
also in the data space, possibly with a different word length than in
the instruction space.

Only if you have flash memory only in instruction space, it might make
sense to have some instructions to copy the initial constant values
from instruction space to data space at startup, but do you really
need instruction page data access after that ?

On cached cores both
I&D caches connect to the same main memory bus.

How does this change anything ?


So I'm not sure what you mean with reduced hardware flexibility? The only
drawback some Harvards have is not automatically supporting self modifying
code,

Self modifying code was an issue in the 1950's when the computers did
not have a decent index register, but after that, how many people did
actually use it ?

but that is a software issue and only applies to cached cores.

The last time I have seen a reference to self modifying code was in
the 1970's, when the VAX processor handbook stated that you should
perform a return from subroutine instruction, until the (self)modified
code was actually executed.

The Harvard architecture is nice, if the code and instruction length
is different or if the code and instruction size is about the same,
e.g. 64 KiB for instruction and 64 Kib for data with a 16 bit word
length.

Paul

.

Relevant Pages