Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics

"Jim Granville" wrote...
Bill Giovino wrote:

"Jim Granville" wrote...

I'm with Jon on this, the semantics matter little; but it would be
good to answer the simple question "Can it execute code from RAM?"
- in some systems, that is useful.


In the case of my original article:
http://www.microcontroller.com/news/arm_cortex_stm.asp
the answer is YES - the ST part can execute code from RAM off the data (system) bus.
Of
course, there will be extra cycles.

In some parts, RAM CODE execution is promoted for speed (due to slower
FLASH speeds).
Is that not the case in the ST device Core/RAM/FLASH combination ?

-jg

Good question... in the ST part, if you are running out of Flash at zero wait states,
then you are getting simultaneous fetches from both data & address buses - taking full
advantage of the Harvard (ahem!) architecture gets you *mostly* single-cycle execution.

But for the same example, if you are running out of RAM, then you are using the same bus
for instructions and data, you lose the advantages of the Harvard architecture and so
it's slower.

However, if you are running out of Flash with the CPU at a higher speed than the Flash,
and so the Flash requires wait states while taking advantage of the Harvard
architecture - the speed compared to running instructions & data out of RAM off the data
bus and so there are extra cycles the answer is - it depends...


.

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