Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics

On Jun 22, 7:34 pm, "Wilco Dijkstra" <Wilco_dot_Dijks...@xxxxxxxxxxxx>
wrote:
"rickman" <gnu...@xxxxxxxxx> wrote in messagenews:1182540547.184518.91830@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
The data *** says it requires one wait state from 24 to 48 MHz and 2
wait states above 48 MHz. So compared to the Luminary parts running
at 50 MHz with *NO* wait states, I say the ST M3 parts are dogs.

It's not that bad. Cortex-M3 has a prefetch buffer and branch prediction. This
means that the cost of a single waitstate can be hidden for conditional branches,
ie. only indirect branches have a penalty. With 2 wait states the branch prediction
only works on unconditional branches, so you'll get a slowdown. However you can
change loops to use an unconditional branch at the end so they run at the speed
of zero-wait state memory.

I don't follow what you are saying at all. Branch prediction relates
to pipelining. I don't see how it relates to wait states. The
required wait states are added because of a fundamental limitation in
the bandwidth of the Flash memory. You can look-ahead all you want,
but you can still only return one word from Flash per 3 clock cycles
when running at full speed. Unless the Flash word width is increased
(as in the NXP designs) or the instruction size is reduced (many
Cortex M3 instructions are 16 bits, but they would need to be 10 bits
with two wait states and 32 bit memory) this will limit performance in
the Cortex M3.

Am I completely missing something? I always leave that possibility
open...


The power consumption is not great either, at least not compared to
parts like Atmel SAM7. The advertisement says it gets "0.5 mA/MHz in
RUN mode from Flash", but this is not very accurate. The power curve
does not have a 0.5 mA/MHz slope. The STM32F103 data *** shows
higher current per MHz at low clock speeds with a Y intercept of about
9 mA. I think the lower mA/MHz at higher clock speeds reflects the
lower MIPS available due to the required wait states.

It is the flash power consumption. When you add wait states the power
consumption flash drops to 50% (1 wait state) or 33% (2 wait states). Ie.
the flash has identical power consumption at 24, 48 and 72MHz.

Of course the secondary effect of adding wait states is the core slows down
and so uses less power. Based on their numbers I estimate the slowdown is
between 10 and 15% - not too bad for 2 wait states.

Yes, that is all pretty obvious. But it does not address the point of
the Y intercept being a hefty 9 mA. This is not as high as the Analog
Devices ARM parts, but it is significant. It means you need to use
modes and hardware features to get better power savings compared to
just slowing the clock which is much simpler to do.


Accounting for
that, the mA/MHz ranges from 0.54 at 24 MHz to 0.88 at 72 MHz. I
think this may be better than the Luminary Stellaris parts, but not as
good as the Atmel SAM7 parts which are claimed to be a true 0.5 mA/MHz
with very low static current in the uA range. I have not looked at
the newer Luminary parts in detail.

I calculate 40mA at 72MHz, so 0.56mA/MHz. Not quite 0.5, but close.
But I don't see where you get the idea they are worse than SAM7. I'm not sure
what part you were comparing with, but the SAM7A3 (also CAN and USB like
STM32F103) shows 70mA at 60MHz, or more than twice at the same frequency.

The SAM7A3 is one of the oldest SAM7 parts and is not a useful basis
for comparison. Personally, I do not expect to have a use for the CAN
controller and I don't expect it was running when the power
measurements were made. I was using the SAM7S parts as a point of
comparison. I have a spread *** that was provided by Atmel which
shows the power rating of the CPU since you can control all the
various power consuming sections. Ignoring the peripherals, the CPU
(with PLL running) consumes 0.5 mA/MHz with a very small Y intercept
(as I initially said).

The power for the STM32 is from the data *** and includes basic
power to the peripherals, although since they are not performing work
the power they draw is less than typical. So the comparison is not
perfect.


Now consider that an M3 runs twice as fast as a SAM7 at the same frequency,
so the MIPS/Watt is 4 times as good!

How do you support the claim that the M3 runs twice as fast as the
SAM7 at the same frequency??? Maybe I don't want to know...

I have not seen anyone claim that the M3 runs twice as fast as an ARM7
clock for clock. I don't even think ARM claims that. I seem to
recall that after all the hoopla is removed, you might see from 10% to
25% speedup from the ARM7 to the M3 depending on your application. If
you disagree on this basic point, then I think we should not discuss
it further. I have seen it discussed before ad nauseum with no hard
information to support any given number.


Actually, I guess a power factor would be required for the SAM7 parts
as well since they run with one wait state at their top speed. So
maybe the STM32 part do better on power than I realized!

If you're trying to compare MIPS/Watt don't forget that different cores running
at the same frequency do not run at the same speed.

Yes, but that is a small delta compared to adding waitstates with a 2x
or 3x reduction in performance and therefore the same effect on power
efficiency.


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